IP Library › Granted Patent US 11,669,143
Granted Patent B2
US 11,669,143 · App. 17/452,146 · Granted Jun 6, 2023

Managing a dynamic total power level for an information handling system

Inventors: Qinghong He (Austin, TX); Tse An Chu (Taipei, TW); Thomas A. Shows (Leander, TX); Travis C. North (Cedar Park, TX)
Assignee: Dell Products L.P.
G06F1/3234G06F1/206G06F1/3206G06T1/20
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Quick Facts
Patent No.
US 11,669,143
App. No.
17/452,146
Granted
Jun 6, 2023
Kind
B2
Abstract

In one embodiment, a method for managing a dynamic total power level for an information handling system includes: identifying, by a power manager of the information handling system, a first power level associated with a processor subsystem of the information handling system, the first power level based on a cooling capacity associated with the information handling system; identifying, by the power manager, a second power level associated with a graphics processing unit of the information handling system, the second power level based on a performance associated with the processor subsystem; determining, by the power manager, the dynamic total power level based on the first power level and the second power level; and modifying, by the power manager, a fixed total power level based on the dynamic total power level, the dynamic total power level causing the processor subsystem and the GPU to operate within the dynamic total power level.

Claims (63)

1. A method for managing a dynamic total power level for an information handling system, the method comprising:

identifying, by a power manager of the information handling system, a first power level associated with a processor subsystem of the information handling system, the first power level based on a cooling capacity associated with the information handling system;

identifying, by the power manager, a second power level associated with a graphics processing unit (GPU) of the information handling system, the second power level based on a performance associated with the processor subsystem; and

determining, by the power manager, the dynamic total power level based on the first power level and the second power level; and

modifying, by the power manager, a fixed total power level based on the dynamic total power level, the dynamic total power level causing the processor subsystem and the GPU to operate within the dynamic total power level.

2. The method of claim 1 , further comprising:

identifying, by the power manager, a change in the first power level associated with the processor subsystem; and

modifying, by the power manager, the dynamic total power level based on the change in the first power level.

3. The method of claim 2 , wherein modifying the dynamic total power level based on the change in the first power level comprises:

determining, by the power manager, that the change in the first power level comprises an increase in the first power level; and

causing, by the power manager, the dynamic total power level to increase based on the increase in the first power level.

4. The method of claim 2 , wherein modifying the dynamic total power level based on the change in the first power level comprises:

determining, by the power manager, that the change in the first power level comprises a decrease in the first power level; and

causing, by the power manager, the dynamic total power level to decrease based on the decrease in the first power level.

5. The method of claim 1 , wherein determining the dynamic total power level based on the first power level and the second power level comprises:

adding, by the power manager, the first power level to the second power level to generate a sum comprising the dynamic total power level.

6. The method of claim 1 , wherein identifying the first power level associated with the processor subsystem comprises:

accessing, by the power manager, a memory of the information handling system, the memory storing a plurality of power profiles associated with the processor subsystem; and

determining, by the power manager, a current power profile of the plurality of power profiles, the current power profile indicating the first power level.

7. The method of claim 6 , wherein the plurality of power profiles associated with the processor subsystem includes:

a memory-mapped input output (MMIO) power profile;

a model-specific register (MSR) power profile; and

a platform environment control interface (PECI) power profile.

8. The method of claim 1 , wherein determining the dynamic total power level based on the first power level and the second power level comprises:

accessing, by the power manager, a memory of the information handling system, the memory including a look up table storing a plurality of power profiles associated with the processor subsystem, each of the plurality of power profiles including a plurality of first power levels associated with the processor subsystem, each of the plurality of first power levels corresponding to a modified second power level associated with the GPU and a modified dynamic total power level;

determining, by the power manager, a current power profile of the plurality of power profiles associated with the processor subsystem;

identifying, by the power manager, a current first power level of the plurality of first power levels associated with the processor subsystem;

selecting, by the power manager, the modified second power level from the look up table based on the current first power level; and

selecting, by the power manager, the modified dynamic total power level from the look up table based on the modified second power level.

9. The method of claim 1 , wherein the cooling capacity associated with the information handling system is based on a skin temperature associated with the information handling system.

10. An information handling system, comprising:

a graphics processing unit (GPU);

a processor subsystem including one or more processors; and

one or more computer-readable non-transitory storage media coupled to one or more of the processors and comprising instructions operable when executed by one or more of the processors to cause the system to:

identify a first power level associated with the processor subsystem, the first power level based on a cooling capacity associated with the information handling system;

identify a second power level associated with the GPU, the second power level based on a performance associated with the processor subsystem;

determine a dynamic total power level based on the first power level and the second power level; and

modify a fixed total power level based on the dynamic total power level, the dynamic total power level causing the processor subsystem and the GPU to operate within the dynamic total power level.

11. The information handling system of claim 10 , wherein the processors are further operable when executed to:

identify a change in the first power level associated with the processor subsystem; and

modify the dynamic total power level based on the change in the first power level.

12. The information handling system of claim 11 , wherein to modify the dynamic total power level based on the change in the first power level, the processors are further operable when executed to:

determine that the change in the first power level comprises an increase in the first power level; and

cause the dynamic total power level to increase based on the increase in the first power level.

13. The information handling system of claim 11 , wherein to modify the dynamic total power level based on the change in the first power level, the processors are further operable when executed to:

determine that the change in the first power level comprises a decrease in the first power level; and

cause the dynamic total power level to decrease based on the decrease in the first power level.

14. The information handling system of claim 10 , wherein to determine the dynamic total power level based on the first power level and the second power level, the processors are further operable when executed to:

add the first power level to the second power level to generate a sum comprising the dynamic total power level.

15. The information handling system of claim 10 , wherein to identify the first power level associated with the processor subsystem, the processors are further operable when executed to:

access a memory of the information handling system, the memory storing a plurality of power profiles associated with the processor subsystem; and

determine a current power profile of the plurality of power profiles, the current power profile indicating the first power level.

16. The information handling system of claim 15 , wherein the plurality of power profiles associated with the processor subsystem includes:

a memory-mapped input output (MMIO) power profile;

a model-specific register (MSR) power profile; and

a platform environment control interface (PECI) power profile.

17. The information handling system of claim 10 , wherein to determine the dynamic total power level based on the first power level and the second power level, the processors are further operable when executed to:

access a memory of the information handling system, the memory including a look up table storing a plurality of power profiles associated with the processor subsystem, each of the plurality of power profiles including a plurality of first power levels associated with the processor subsystem, each of the plurality of first power levels corresponding to a modified second power level associated with the GPU and a modified dynamic total power level;

determine a current power profile of the plurality of power profiles associated with the processor subsystem;

identify a current first power level of the plurality of first power levels associated with the processor subsystem;

select the modified second power level from the look up table based on the current first power level; and

select the modified dynamic total power level from the look up table based on the modified second power level.

18. The information handling system of claim 10 , wherein the cooling capacity associated with the information handling system is based on a skin temperature associated with the information handling system.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 25, 2021
From: HE, QINGHONG; CHU, TSE AN; SHOWS, THOMAS A.; NORTH, TRAVIS C.
To: DELL PRODUCTS L.P.
Reel/Frame 057901/0736 →
Continuity (1)
Related Publication 20230126809A1 · Apr 27, 2023