Automatic test pattern generation (ATPG) for parametric faults

1. A method, comprising:

determining a set of measurements for a metric of an integrated circuit (IC) design by simulating the IC design over a set of random samples of random variables;

determining a first set of measurement margins based on the set of measurements, wherein each measurement margin corresponds to a difference between a measurement and a threshold;

constructing a Gaussian process (GP) model based on the first set of measurement margins, wherein the GP model predicts a second set of measurement margins that would be generated by simulating the IC design; and

determining, by a processor, a set of failure events for the IC design using the GP model, wherein each failure event corresponds to a set of values of the random variables that is expected to cause the metric of the IC design to violate the threshold.

2. The method of claim 1 , wherein the random variables include a process variable, a voltage variable, and a temperature variable.

3. The method of claim 1 , wherein the determining the set of failure events for the IC design comprises:

constructing an acquisition function; and

using an optimization technique to adaptively determine samples of the random variables by using the acquisition function.

4. The method of claim 3 , wherein the acquisition function enables exploration of multiple failure regions of a search space defined by the random variables.

5. The method of claim 1 , further comprising determining a probability density function based on the set of failure events.

6. The method of claim 5 , further comprising:

determining a weight function based on the probability density function, wherein the weight function is associated with an importance sampling process; and

using the importance sampling process to calculate a failure rate of the IC design.

7. The method of claim 6 , further comprising using an optimization technique to determine a set of excitation waveforms based on maximizing the failure rate of the IC design.

8. The method of claim 7 , wherein each excitation waveform in the set of excitation waveforms is represented as a piece-wise linear function, and the method further comprises testing parametric faults in the IC design using the set of excitation waveforms.

9. A system, comprising:

a memory storing instructions; and

a processor, coupled with the memory and to execute the instructions, the instructions when executed cause the processor to:

determine a set of measurements for a metric of an integrated circuit (IC) design by simulating the IC design over a set of random samples of random variables;

determine a first set of measurement margins based on the set of measurements, wherein each measurement margin corresponds to a difference between a measurement and a threshold;

construct a Gaussian process (GP) model based on the first set of measurement margins, wherein the GP model predicts a second set of measurement margins that would be generated by simulating the IC design; and

determine a set of failure events for the IC design using the GP model, wherein each failure event corresponds to a set of values of the random variables that is expected to cause the metric of the IC design to violate the threshold.

10. The system of claim 9 , wherein the random variables include a process variable, a voltage variable, and a temperature variable.

11. The system of claim 9 , wherein the determining the set of failure events for the IC design comprises:

constructing an acquisition function; and

using an optimization technique to adaptively determine samples of the random variables by using the acquisition function.

12. The system of claim 11 , wherein the acquisition function enables exploration of multiple failure regions of a search space defined by the random variables.

13. The system of claim 9 , wherein the instructions when executed cause the processor to determine a probability density function based on the set of failure events.

14. The system of claim 13 , wherein the instructions when executed cause the processor to:

determine a weight function based on the probability density function, wherein the weight function is associated with an importance sampling process; and

use the importance sampling process to calculate a failure rate of the IC design.

15. The system of claim 14 , wherein the instructions when executed cause the processor to use an optimization technique to determine a set of excitation waveforms based on maximizing the failure rate of the IC design.

16. The system of claim 15 , wherein each excitation waveform in the set of excitation waveforms is represented as a piece-wise linear function, and wherein the instructions when executed cause the processor to test parametric faults in the IC design using the set of excitation waveforms.

17. A non-transitory computer-readable medium comprising stored instructions, which when executed by a processor, cause the processor to:

determine a set of measurements for a metric of an integrated circuit (IC) design by simulating the IC design over a set of random samples of random variables;

determine a first set of measurement margins based on the set of measurements, wherein each measurement margin corresponds to a difference between a measurement and a threshold;

construct a Gaussian process (GP) model based on the first set of measurement margins, wherein the GP model predicts a second set of measurement margins that would be generated by simulating the IC design; and

determine a set of failure events for the IC design using the GP model, wherein each failure event corresponds to a set of values of the random variables that is expected to cause the metric of the IC design to violate the threshold.

18. The non-transitory computer-readable medium of claim 17 , wherein the random variables include a process variable, a voltage variable, and a temperature variable.