Storage device and method of operating the same
A method of operating a storage device including a neural network processor includes outputting, by a controller device, a trigger signal instructing the neural network processor to perform a neural network operation in response to a command from a host device, requesting, by a neural network processor, target model data about parameters of a target model and instruction data for instructing the neural network operation to a memory device storing the target model data and the instruction data in response to the trigger signal, receiving, by the neural network processor, the target model data and the instruction data from the memory device and outputting, by the neural network processor, inference data based on the target model data and the instruction data.
1. A method of operating a storage device comprising a neural network processor, the method comprising:
outputting, by a controller device, a signal instructing the neural network processor to perform a neural network operation based on a command from a host device;
requesting, by the neural network processor, target model data and instruction data from a memory device storing the target model data and the instruction data based on the signal, the target model data corresponding to parameters of a target model and the instruction data for performing the neural network operation based on the target model;
receiving, by the neural network processor, the target model data and the instruction data from the memory device; and
outputting, by the neural network processor, inference data based on the target model data and the instruction data.
2. The method of claim 1 , wherein the requesting the target model data and the instruction data comprises:
designating a page address of the memory device, and
requesting the target model data and the instruction data that are written together in the page address.
3. The method of claim 2 , wherein the requesting the target model data and the instruction data, comprises:
requesting the target model data and the instruction data from a next page address when the instruction data written in the designated page address includes information corresponding to the next page address.
4. Method of claim 1 , wherein the outputting the inference data comprises outputting result data corresponding to each layer of the target model by performing a series of operations on input data based on the instruction data.
5. The method of claim 4 , wherein the requesting the target model data and the instruction data comprises requesting first layer data corresponding to a first layer of the target model and the instruction data from the memory device based on the signal.
6. The method of claim 5 , wherein the outputting the inference data comprises:
receiving the first layer data and the instruction data from the memory device, and generating first result data by performing the neural network operation on the first layer; and
requesting, by the neural network processor, second layer data from the memory device based on the first result data.
7. The method of claim 6 , wherein the outputting the inference data comprises:
generating a second result data by performing the neural network operation on a second layer by using the first result data as input data; and
generating the second result data as the inference data based on a determination that the second layer is a final layer of the target model.
8. The method of claim 1 , wherein the outputting the inference data comprises dividing the target model data and the instruction data, and respectively storing the target model data and the instruction data in separate buffer memories.
9. The method of claim 1 , further comprising storing the target model data and the instruction data together in each page of the memory device.
10. The method of claim 9 , wherein the storing of the target model data and the instruction data comprises storing layer data corresponding to each layer of the target model and the instruction data in each page group.
11. The method of claim 9 , wherein the storing of the target model data and the instruction data comprises identifying a memory in which layer data corresponding to each layer of the target model and the instruction data are to be stored, based on an arithmetic intensity for performing the neural network operation on the each layer of the target model.
12. The method of claim 11 , wherein the identifying the memory in which the layer data and the instruction data are to be stored comprises:
storing first layer data in a first memory based on a first arithmetic intensity of a first layer being less than a threshold value, and
storing the first layer data in a second memory based on the first arithmetic intensity of the first layer being greater than or equal to the threshold value.
13. The method of claim 9 , wherein, based on the instruction data including page sequence information corresponding to a plurality of pages, the storing of the target model data and the instruction data comprises writing identification bits indicating page ranges in which the target model data is written, in a first page and a final page of the plurality of pages.
14. The method of claim 9 , wherein the storing the target model data and the instruction data comprises storing an address of a page related to the target model data in the controller device or the neural network processor.
15. A storage device comprising:
a controller device configured to output a first signal instructing a neural network operation based on a command from a host device;
a memory device configured to store target model data corresponding to a parameter of a target model in a first page area of a page in the memory device and store instruction data for instructing the neural network operation in a second page area of the page in the memory device; and
a neural network processor configured to:
output a second signal to the memory device based on the first signal, the second signal including a request for the target model data and the instruction data from the memory device,
receive the target model data and the instruction data from the memory device, and
output inference data based on the target model data and the instruction data.
16. The storage device of claim 15 , wherein the memory device is further configured to:
designate a page address, and
provide target model data and instruction data, which correspond to the designated page address, to the neural network processor.
17. The storage device of claim 15 , wherein the neural network processor is further configured to:
perform a series of operations on input data based on first layer data corresponding to a first layer of the target model and the instruction data,
generate result data corresponding to the first layer of the target model, and
request second layer data from the memory device in response to the generating of the result data.
18. A memory device comprising:
a memory cell array comprising a plurality of pages; and
a memory controller device configured to:
perform a read operation on a target page, among the plurality of pages, based on a read command for the target page, and
output the target page,
wherein each of the plurality of pages comprises:
a first page area configured to store target model data corresponding to a target model on which a neural network operation is to be performed; and
a second page area configured to store instruction data for instructing the neural network operation on the target model.
19. The memory device of claim 18 , wherein the memory cell array comprises a plurality of page groups configured to store layer data corresponding to each layer of the target model and the instruction data.
20. The memory device of claim 19 , wherein the plurality of page groups store layer data corresponding to layers of which an arithmetic intensity for performing the neural network operation is less than a threshold value and the instruction data.