Tunable CMOS circuit, template matching module, neural spike recording system, and fuzzy logic gate
A tunable CMOS circuit comprising a CMOS element and a tunable load. The CMOS element is configured to receive in an analogue input signal. The tunable load is connected to the CMOS element and configured to set a switch point of the CMOS element. The CMOS element is configured to output an output current that is largest when the analogue input signal is equal to the switch point. The combination of a CMOS element with a tunable load may also provide a hardware implementation of fuzzy logic. A fuzzy logic gate comprises an input node, a CMOS logic gate including a tunable load, and an output node. The input node is configured to receive an analogue input signal. The CMOS logic gate is connected to the input node. The tunable load is provided on a current path connected to the output node. The output node is configured to output an analogue output signal.
1. A tunable complementary metal oxide semiconductor (CMOS) circuit comprising
a CMOS element configured to receive an analogue input signal, and
a tunable load connected to the CMOS element and configured to set a switch point of the CMOS element,
wherein the CMOS element is configured to output an output current, the output current being largest when the analogue input signal is equal to the switch point.
2. The tunable CMOS circuit of claim 1 , wherein the tunable load comprises one or more memristors.
3. The tunable CMOS circuit of claim 1 , wherein:
the CMOS element comprises a first CMOS stage and a second CMOS stage,
the first CMOS stage is configured to receive the analogue input,
the output of the first CMOS stage is connected to the input of the second CMOS stage, and
the second CMOS stage is configured to draw a current that is largest when the analogue input signal is equal to the switch point.
4. The tunable CMOS circuit of claim 3 , wherein:
the first CMOS stage comprises a CMOS inverter, and/or
the second CMOS stage comprises a CMOS inverter.
5. The tunable CMOS circuit of claim 3 , wherein:
the CMOS element comprises an output stage configured to output the output current, and
the output stage is configured to output an output current that is proportional to the current drawn by the second CMOS stage, optionally wherein the output stage comprises a current mirror.
6. The tunable CMOS circuit of claim 3 , wherein:
the first CMOS stage is configured to output a midpoint signal,
the second CMOS stage is configured to draw a current that is largest when the midpoint signal is at a predetermined fixed value, and
the tunable load is connected to the first CMOS stage such that the first CMOS stage outputs a midpoint signal equal to the predetermined fixed value when the analogue input signal is equal to the switch point set by the tunable load.
7. The tunable CMOS circuit of claim 3 , wherein:
the first CMOS stage is configured to output a midpoint signal, and
the tunable load is connected to the second CMOS stage so as to set the value of the midpoint signal at which the current drawn by the second CMOS stage is largest.
8. The tunable CMOS circuit of claim 7 , wherein the tunable load is connected in series to the second CMOS stage.
9. The tunable CMOS circuit of claim 1 , wherein the CMOS element consists of six transistors and two memristors.
10. The tunable CMOS circuit of claim 3 , further comprising an input range setter connected to the first CMOS stage, the input range setter being configured to match an input signal range of the first CMOS stage to an input signal range of the second CMOS stage.
11. A method of using the tunable complementary metal oxide semiconductor (CMOS) circuit of claim 1 , the method comprising:
programming the tunable load to set the switch point of the tunable CMOS circuit,
applying an analogue signal to the tunable CMOS circuit, and
measuring the output current of the tunable CMOS circuit.