IP Library › Granted Patent US 11,670,625
Granted Patent B2
US 11,670,625 · App. 16/979,592 · Granted Jun 6, 2023

Imaging unit having a stacked structure and electronic apparatus including the imaging unit

Inventor: Masahiko Yukawa (Kanagawa, JP)
Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
H01L25/167H01L24/08H01L24/32H01L27/1469H01L27/14634H01L27/14636H01L2224/08145H01L2224/08221H01L2224/32145
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 11,670,625
App. No.
16/979,592
Granted
Jun 6, 2023
Kind
B2
Abstract

Provided is a solid-state imaging unit that includes a stacked structure including a sensor substrate and a circuit board. The sensor board has an effective pixel region where an imaging device is disposed. The imaging device includes a plurality of pixels and is configured to receive external light in each of the pixels to generate a pixel signal. The circuit board includes a chip including a first portion and a second portion that are integrated with each other. The first portion includes a signal processing circuit that performs signal processing of the pixel signal. The second portion is disposed at a position different from a position of the first portion in an in-plane direction. Here, both the first portion and the second portion are disposed to overlap the effective pixel region in a stacking direction of the sensor board and the circuit board.

Claims (48)

1. An imaging unit, comprising

a stacked structure that includes:

a sensor board that includes having an effective pixel region, wherein

the effective pixel region includes an imaging device,

the imaging device includes a plurality of pixels, and

the imaging device is configured to receive external light in each pixel of the plurality of pixels to generate a pixel signal; and

a circuit board that includes a chip, wherein

the chip includes a first portion and a second portion,

the first portion is integrated with the second portion,

the first portion includes a signal processing circuit,

the signal processing circuit includes a first semiconductor device configured to execute signal processing of the pixel signal,

the second portion is at a position different from a position of the first portion in an in-plane direction on the circuit board,

the second portion includes a dummy circuit including a second semiconductor device, and

both the first portion and the second portion overlap the effective pixel region in a stacking direction of the sensor board and the circuit board.

2. The imaging unit according to claim 1 , wherein an outer edge of the chip one of:

overlaps an outer edge of the effective pixel region in the stacking direction of the sensor board and the circuit board, or

is on an outer side with respect to the outer edge of the effective pixel region in the stacking direction of the sensor board and the circuit board.

3. The imaging unit according to claim 1 , further comprising a wiring line configured to electrically couple the imaging device to the signal processing circuit.

4. The imaging unit according to claim 3 , wherein

the wiring line includes a first wiring-line portion and a second wiring-line portion,

the sensor board includes the first wiring-line portion,

the first wiring-line portion is exposed on a surface of the sensor board,

the circuit board includes the second wiring-line portion,

the second wiring-line portion is exposed on a surface of the circuit board, and

the first wiring-line portion is bonded to the second wiring-line portion.

5. The imaging unit according to claim 1 , wherein

the circuit board further includes:

a single semiconductor substrate; and

a circuit formation layer on the single semiconductor substrate, and

the circuit formation layer includes the signal processing circuit and the dummy circuit.

6. The imaging unit according to claim 1 , wherein

the stacked structure further includes a third board on an opposite side of the circuit board, and

the circuit board is between the third board and the sensor board.

7. The imaging unit according to claim 1 , wherein the signal processing circuit further includes at least one of a logic circuit, a memory circuit, a power circuit, an image signal compression circuit, a clock circuit, or an optical communication conversion circuit.

8. An electronic apparatus, comprising:

an imaging unit, wherein the imaging unit includes:

a stacked structure that includes:

a sensor board that includes having an effective pixel region, wherein

the effective pixel region includes an imaging device,

the imaging device includes a plurality of pixels, and

the imaging device is configured to receive external light in each pixel of the plurality of pixels to generate a pixel signal; and

a circuit board that includes a first portion and a second portion, wherein

the first portion is integrated with the second portion,

the first portion includes a signal processing circuit,

the signal processing circuit includes a first semiconductor device configured to execute signal processing of the pixel signal,

the second portion is at a position different from a position of the first portion in an in-plane direction on the circuit board,

the second portion includes a dummy circuit including a second semiconductor device, and

both the first portion and the second portion overlap the effective pixel region in a stacking direction of the sensor board and the circuit board.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 10, 2020
From: YUKAWA, MASAHIKO
To: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
Reel/Frame 053731/0880 →
Priority Claims (1)
JP JP2018-051318 · Mar 19, 2018 · national
Continuity (1)
Related Publication 20210005658A1 · Jan 7, 2021