Method of forming fully strained channels

1. A method comprising:

forming an N well and a P well in a substrate;

depositing a first layer having silicon over the N well and the P well;

depositing a first dielectric layer over the first layer;

forming a resist pattern over the first dielectric layer, the resist pattern providing an opening directly above the N well;

etching the first dielectric layer and the first layer through the opening, leaving a first portion of the first layer over the N well;

removing the resist pattern;

epitaxially growing a second layer having silicon germanium (SiGe) over the first portion of the first layer, wherein the epitaxially growing the second layer includes steps of (a) performing a baking process, (b) depositing a silicon seed layer, and (c) depositing a SiGe layer over the silicon seed layer, wherein the steps (a), (b), and (c) are performed in an isothermal process; depositing a second dielectric layer over the first dielectric layer and over the SiGe layer;

performing a first chemical mechanical polishing (CMP) process to the second dielectric layer and the first dielectric layer; and

performing a second CMP process to the SiGe layer and the first layer.

2. The method of claim 1 , wherein the steps (a), (b), and (c) are performed at a temperature in a range of about 650° C. to 750° C.

3. The method of claim 1 , wherein the baking process is performed in H 2 ambient.

4. The method of claim 1 , further comprising:

patterning the first layer and the P well to form first fins;

patterning the SiGe layer and the N well to form second fins; and

forming an isolation feature to isolate bottom portions of the first fins and the second fins.

5. The method of claim 4 , further comprising:

forming n-type FinFET over the first fins and above the isolation feature; and

forming p-type FinFET over the second fins and above the isolation feature.

6. The method of claim 1 , before the depositing of the first layer, further comprising:

forming a portion of an alignment mark into the substrate.

7. The method of claim 1 , before the depositing of the first dielectric layer, further comprising:

forming an alignment trench into the first layer.

8. The method of claim 1 , wherein the second layer is epitaxially grown such that its topmost surface is higher than a top surface of the first layer and is lower than a top surface of the first dielectric layer.

9. The method of claim 1 , wherein temperatures at which the steps (a), (b), and (c) are performed vary less than +/−10° C.

10. The method of claim 1 , further comprising:

before the forming of the N well and P well, forming an alignment mark in the substrate, wherein a top surface of the N well and P well is coplanar with a top surface of the alignment mark.

11. A method comprising:

providing a substrate;

depositing a silicon layer over the substrate;

etching an alignment trench into the silicon layer;

depositing a first oxide layer over the silicon layer and in the alignment trench, wherein the first oxide layer partially fills the alignment trench and leaves a remaining portion of the alignment trench unfilled;

forming an etch mask over the first oxide layer, wherein the etch mask fully fills the remaining portion of the alignment trench and has an opening directly above a first portion of the silicon layer;

etching the first oxide layer and the first portion of the silicon layer through the opening, thereby forming a first trench;

removing the etch mask; and

epitaxially growing a second layer having silicon germanium (SiGe) in the first trench, wherein the epitaxially growing the second layer includes steps of (a) performing a baking process, (b) depositing a silicon seed layer, and (c) depositing a SiGe layer on the silicon seed layer, wherein the steps (a), (b), and (c) are performed in an isothermal process.

12. The method of claim 11 , further comprising:

depositing a second oxide layer over the first oxide layer and over the SiGe layer;

performing a first chemical mechanical polishing (CMP) process to the first and the second oxide layers; and

performing a second CMP process to the SiGe layer.

13. The method of claim 11 , wherein the steps (a), (b), and (c) are performed at a temperature in a range of about 650° C. to 750° C.

14. The method of claim 11 , wherein the second layer is epitaxially grown such that its topmost surface is higher than a top surface of the silicon layer and is about even with or lower than a top surface of the first oxide layer.

15. The method of claim 11 , wherein the baking process is performed in H 2 ambient.

16. The method of claim 11 , wherein the baking process is performed in ambient having N 2 , Ar, He, or a combination thereof.

17. The method of claim 11 , wherein the etching of the first portion of the silicon layer through the opening leaves a layer of the first portion of the silicon layer in the first trench.

18. A method comprising:

providing a substrate;

forming an alignment mark in the substrate;

forming an N well and a P well in the substrate based on a distance from the alignment mark:

forming a first layer having silicon over the N well, the P well, and the alignment mark;

etching the first layer to form an alignment trench exposing the alignment mark;

forming a first dielectric layer over the first layer, the first dielectric layer filling the alignment trench;

etching the first dielectric layer and the first layer above the N well, leaving a first portion of the first layer over the N well and a second portion of the first layer over the P well, wherein the first portion of the first layer is thinner than the second portion of the first layer;

while the first dielectric layer covering the second portion of the first layer, epitaxially growing a second layer having silicon germanium (SiGe) over the first portion of the first layer, wherein the epitaxially growing the second layer includes steps of (a) performing a baking process, (b) depositing a silicon seed layer, and (c) depositing a SiGe layer over the silicon seed layer, wherein the steps (a), (b), and (c) are performed in an isothermal process;

patterning the second portion of the first layer and the P well to form first fins; and

patterning the second layer, the first portion of the first layer, and the N well to form second fins.

19. The method of claim 18 , wherein the second layer is epitaxially grown such that its topmost surface is higher than a top surface of the second portion of the first layer and is lower than a top surface of the first dielectric layer.

20. The method of claim 18 , before the patterning of the second portion of the first layer and the P well and before the patterning of the second layer, the first portion of the first layer, and the N well, further comprising:

depositing a second dielectric layer over the first dielectric layer and over the second layer;

performing a first chemical mechanical polishing (CMP) process to the second dielectric layer and the first dielectric layer; and

performing a second CMP process to the second layer and the first layer.