Fin and gate dimensions for optimizing gate formation

1. A method comprising:

forming a first multi-fin structure having a first pitch in a first channel region and a second multi-fin structure having a second pitch in a second channel region, wherein the first pitch is greater than the second pitch;

forming a first gate structure over the first channel region of the first multi-fin structure, wherein the first gate structure includes a first gate dielectric having a first thickness and a first gate electrode over the first gate dielectric;

forming a second gate structure over the second channel region of the second multi-fin structure, wherein the second gate structure includes a second gate dielectric having a second thickness and a second gate electrode over the second gate dielectric, wherein the second thickness is less than the first thickness; and

configuring a ratio of the first thickness to the second thickness and a ratio of the first pitch to the second pitch to provide a common process window for formation of the first gate electrode and the second gate electrode at the same time, wherein:

the ratio of the first pitch to the second pitch depends on the ratio of the first thickness to the second thickness,

a first spacing between the first gate dielectric disposed on directly adjacent first fins of the first multi-fin structure depends on the first thickness and the first pitch,

a second spacing between the second gate dielectric disposed on directly adjacent second fins of the second multi-fin structure depends on the second thickness and the second pitch, and

the common process window for forming the first gate electrode and the second gate electrode at the same time is provided when the first spacing between the first gate dielectric disposed on directly adjacent first fins of the first multi-fin structure is substantially the same as the second spacing between the second gate dielectric disposed on directly adjacent second fins of the second multi-fin structure.

2. The method of claim 1 , wherein a ratio of the first pitch to the second pitch is about 1.05 to about 1.15.

3. The method of claim 1 , wherein a ratio of the first thickness to the second thickness is about 1.3 to about 1.8.

4. The method of claim 1 , wherein the forming the first gate structure and the forming the second gate structure includes performing a gate replacement process.

5. The method of claim 1 , wherein the first pitch is less than or equal to about 30 nm and the second pitch is less than or equal to about 28 nm.

6. The method of claim 1 , further comprising an input/output (I/O) region and a core region, wherein the first multi-fin structure and the first gate structure are a portion of a transistor disposed in the I/O region and the second multi-fin structure and the second gate structure are a portion of a transistor disposed in the core region.

7. The method of claim 1 , further comprising:

forming a merged first epitaxial source/drain feature over a first source region and a first drain region of first fins of the first multi-fin structure; and

forming a merged second epitaxial source/drain feature over a second source region and a second drain region of second fins of the second multi-fin structure, wherein the ratio of the first pitch to the second pitch is further configured to ensure that epitaxial material grown from at least two directly adjacent first fins of the first multi-fin structure merges when forming the merged first epitaxial source/drain feature.

8. The method of claim 7 , wherein:

the merged first epitaxial source/drain feature is disposed over and spans each of the first fins of the first multi-fin structure and the merged first epitaxial source/drain feature includes at least one gap between directly adjacent first fins; and

the merged second epitaxial source/drain feature is disposed over and spans each of the second fins of the second multi-fin structure and the merged second epitaxial source/drain feature is free of gaps between directly adjacent second fins.

9. A method comprising:

forming a first fin, a second fin, a third fin, and a fourth fin over a substrate, wherein the first fin and the second fin are separated by a first distance in an input/output (I/O) region, the third fin and the fourth fin are separated by a second distance in a logic region, and the first distance is greater than the second distance;

forming an isolation region over a lower portion of the first fin, a lower portion of the second fin, a lower portion of the third fin, and a lower portion of the fourth fin;

forming a first gate structure and a second gate structure, wherein the first gate structure is disposed over a channel region of an upper portion of the first fin and a channel region of an upper portion of the second fin and the second gate structure is disposed over a channel region of an upper portion of the third fin and a channel region of an upper portion of the fourth fin, and further wherein the first gate structure includes a first dummy gate and the second gate structure includes a second dummy gate;

forming merged first epitaxial source/drain features and merged second epitaxial source/drain features, wherein the merged first epitaxial source/drain features are disposed over source/drain regions of the first fin and source/drain regions of the second fin and the merged second epitaxial source/drain features are disposed over source/drain regions of the third fin and source/drain regions of the fourth fin;

forming an interlevel dielectric layer over the merged first epitaxial source/drain features, the merged second epitaxial source/drain features, the first gate structure, and the second gate structure;

removing the first dummy gate from the first gate structure to form a first opening and the second dummy gate from the second gate structure to form a second opening, wherein the first opening exposes the channel region of the upper portion of the first fin and the channel region of the upper portion of the second fin and the second opening exposes the channel region of the upper portion of the third fin and the channel region of the upper portion of the fourth fin; and

forming a first metal gate in the first opening and a second metal gate in the second opening, wherein the first metal gate includes a first gate electrode disposed over a first gate dielectric having a first thickness, the second metal gate includes a second gate electrode disposed over a second gate dielectric having a second thickness, and the first thickness is greater than the second thickness;

configuring a ratio of the first thickness to the second thickness and a ratio of the first distance to the second distance to provide a common process window for forming the first gate electrode and the second gate electrode at the same time and to ensure merging of epitaxial material grown from the first fin and the second fin when forming the merged first epitaxial source/drains and epitaxial material grown from the third fin and the fourth fin when forming the merged second epitaxial source/drains; and

wherein a ratio of the first distance to the second distance accounts for the ratio of the first thickness to the second thickness and the common process window for forming the first gate electrode and the second gate electrode at the same time is provided when a first spacing between the first gate dielectric disposed on the first fin and the second fin that is substantially the same as a second spacing between the second gate dielectric disposed on the third fin and the fourth fin.

10. The method of claim 9 , wherein the first thickness is about 30% greater than the second thickness.

11. The method of claim 9 , wherein the ratio of the first distance to the second distance is about 1.05 to about 1.15 and the ratio of the first thickness to the second thickness is about 1.3 to about 1.8.

12. The method of claim 9 , wherein the first metal gate has a first work function and the second metal gate has a second work function that is different than the first work function.

13. The method of claim 9 , further comprising:

forming a fifth fin over the substrate, wherein the first fin and the fifth fin are separated by the first distance in the I/O region, wherein epitaxial material grown from the fifth fin when forming the merged first epitaxial source/drain features does not merge with the epitaxial material grown from the first fin when forming the merged first epitaxial source/drain features.

14. The method of claim 9 , wherein the first fin and the second fin are disposed over a first doped region of the substrate and the third fin and the fourth fin are disposed over a second doped region of the substrate, the method further comprising:

forming a fifth fin and a sixth fin over a third doped region of the substrate and a seventh fin and an eighth fin over a fourth doped region of the substrate, wherein the fifth fin and the sixth fin are separated by the first distance in the I/O region and the seventh fin and the eighth fin are separated by the second distance in the logic region;

forming the isolation region over a lower portion of the fifth fin, a lower portion of the sixth fin, a lower portion of the seventh fin, and a lower portion of the eighth fin;

forming the first gate structure over a channel region of an upper portion of the fifth fin and a channel region of an upper portion of the sixth fin and forming the second gate structure over a channel region of an upper portion of the seventh fin and a channel region of an upper portion of the eighth fin;

forming third epitaxial source/drain features and fourth epitaxial source/drain features, wherein the third epitaxial source/drain features are disposed over source/drain regions of the fifth fin and source/drain regions of the sixth fin and the fourth epitaxial source/drain features are disposed over source/drain regions of the seventh fin and source/drain regions of the eighth fin;

forming the interlevel dielectric layer over the third epitaxial source/drain features and the fourth epitaxial source/drain features; and

wherein the first opening further exposes the channel region of the upper portion of the fifth fin and the channel region of the upper portion of the sixth fin and the second opening further exposes the channel region of the upper portion of the seventh fin and the channel region of the upper portion of the eighth fin.

15. The method of claim 14 , wherein the first fin and the second fin are a portion of a first transistor, the third fin and the fourth fin are a portion of a second transistor, the fifth fin and the sixth fin are a portion of a third transistor, and the seventh fin and the eighth fin are a portion of a fourth transistor.

16. A method comprising:

forming a first fin-like field effect transistor that includes a first gate structure traversing first fins, wherein the first gate structure includes a first gate dielectric and a first gate electrode;

forming a second fin-like field effect transistor that includes a second gate structure traversing second fins, wherein the second gate structure includes a second gate dielectric and a second gate electrode;

wherein the first fins have a first fin pitch, the second fins have a second fin pitch, and the first fin pitch is greater than the second fin pitch;

wherein the first gate dielectric has a first thickness, the second gate dielectric has a second thickness, and the first thickness is greater than the second thickness;

wherein a ratio of the first fin pitch to the second fin pitch is about 1.05 to about 1.15 and the ratio of the first thickness to the second thickness is about 1.3 to about 1.8; and

wherein the ratio of the first fin pitch to the second fin pitch and the ratio of the first thickness to the second thickness provide a spacing between the first gate dielectric disposed over sidewalls of directly adjacent first fins that is substantially the same as a spacing between the second gate dielectric disposed over sidewalls of directly adjacent second fins, such that a common process window is provided for forming the first gate electrode and the second gate electrode at the same time.

17. The method of claim 16 , wherein the first fin pitch and second fin pitch are both less than about 30 nm.

18. The method of claim 16 , wherein:

the first fin-like field effect transistor includes a merged first epitaxial source/drain feature disposed over and spanning the first fins with at least one interruption between epitaxial material extending from directly adjacent first fins; and

the second fin-like field effect transistor includes a merged second epitaxial source/drain feature disposed over and spanning the second fins without interruption between epitaxial material extending from directly adjacent second fins.

19. The method of claim 16 , further comprising:

forming a third fin-like field effect transistor that includes a third gate structure traversing third fins, wherein the third gate structure includes a third gate dielectric and a third gate electrode;

forming a fourth fin-like field effect transistor that includes a fourth gate structure traversing fourth fins, wherein the fourth gate structure includes a fourth gate dielectric and a fourth gate electrode;

wherein the third fins have a third fin pitch, the fourth fins have a fourth fin pitch, and the third fin pitch is greater than the fourth fin pitch;

wherein the third gate dielectric has a third thickness, the fourth gate dielectric has a fourth thickness, and the third thickness is greater than the fourth thickness; and

wherein a ratio of the third fin pitch to the fourth fin pitch is about 1.05 to about 1.15 and the ratio of the third thickness to the fourth thickness is about 1.3 to about 1.8; and

wherein the ratio of the third fin pitch to the fourth fin pitch and the ratio of the third thickness to the fourth thickness are provide a spacing between the third gate dielectric disposed over sidewalls of directly adjacent third fins that is substantially the same as a spacing between the fourth gate dielectric disposed over sidewalls of directly adjacent fourth fins.

20. The method of claim 16 , wherein the first fin-like field effect transistor is an input/output transistor and the second fin-like field effect transistor is a core transistor.