Silicon channel tempering

1. A semiconductor structure, comprising:

a fin structure over a substrate;

a vertical stack of silicon nanostructures disposed over the fin structure;

inner spacer features interleaving the vertical stack of silicon nanostructures;

an isolation structure disposed around the fin structure;

a germanium-containing interfacial layer wrapping around each of the vertical stack of silicon nanostructures;

a gate dielectric layer wrapping around the germanium-containing interfacial layer; and

a gate electrode layer wrapping around the gate dielectric layer,

wherein the germanium-containing interfacial layer is in contact with the inner spacer features.

2. The semiconductor structure as claimed in claim 1 , further comprising:

a silicon germanium layer between the germanium-containing interfacial layer and each of the vertical stack of silicon nanostructures.

3. The semiconductor structure as claimed in claim 1 , wherein the germanium-containing interfacial layer comprises silicon germanium oxide, germanium oxide, or germanium-doped silicon oxide.

4. The semiconductor structure as claimed in claim 1 , wherein the germanium-containing interfacial layer is disposed on the fin structure.

5. The semiconductor structure as claimed in claim 4 , further comprising:

a silicon germanium layer between the germanium-containing interfacial layer and the fin structure.

6. The semiconductor structure as claimed in claim 1 , wherein a germanium concentration in the germanium-containing interfacial layer is between about 3% and about 4%.

7. A semiconductor device, comprising:

a p-type transistor comprising:

a first fin structure over a substrate and disposed within an isolation feature,

a first plurality of silicon nanostructures disposed over the first fin structure,

a first plurality of inner spacer features interleaving the first plurality of silicon nanostructures,

a first interfacial layer wrapping around each of the first plurality of silicon nanostructures and disposed on and in contact with a top surface of the first fin structure,

a gate dielectric layer wrapping around the first interfacial layer, and

a gate electrode layer wrapping around the gate dielectric layer; and

an n-type transistor comprising:

a second fin structure over the substrate and disposed within the isolation feature,

a second plurality of silicon nanostructures disposed over the second fin structure,

a second plurality of inner spacer features interleaving the second plurality of silicon nanostructures,

a second interfacial layer wrapping around and in contact with each of the second plurality of silicon nanostructures, and disposed on and in contact with at top surface of the second fin structure,

the gate dielectric layer wrapping around the second interfacial layer, and

the gate electrode layer wrapping around the gate dielectric layer,

wherein a composition of the first interfacial layer is different from a composition of the second interfacial layer,

wherein the first interfacial layer comprises silicon and germanium and a germanium content in the first interfacial layer is smaller than 10%,

wherein the first interfacial layer is in contact with the first plurality of inner spacer features,

wherein the second interfacial layer is in contact with the second plurality of inner spacer features.

8. The semiconductor device as claimed in claim 7 , wherein the second interfacial layer is free of germanium.

9. The semiconductor device as claimed in claim 7 , further comprising:

a silicon germanium layer between the first interfacial layer and the first plurality of silicon nanostructures.

10. The semiconductor device as claimed in claim 7 , wherein the first interfacial layer is disposed on the first fin structure.

11. The semiconductor device as claimed in claim 7 , wherein the first plurality of silicon nanostructures consist essentially of silicon.

12. The semiconductor device as claimed in claim 7 ,

wherein the first interfacial layer comprises silicon germanium oxide, germanium oxide, or germanium-doped silicon oxide,

wherein the second interfacial layer comprises silicon oxide.

13. The semiconductor device as claimed in claim 7 , further comprising:

inner spacer features interleaving the first plurality of silicon nanostructures,

wherein the first interfacial layer is in contact with the inner spacer features.

14. The semiconductor device as claimed in claim 7 ,

wherein the p-type transistor further comprises a p-type source/drain feature coupled to the first plurality of silicon nanostructures,

wherein the p-type source/drain feature comprises silicon germanium and a p-type dopant,

wherein the n-type transistor further comprises a n-type source/drain feature coupled to the second plurality of silicon nanostructures,

wherein the n-type source/drain feature comprises silicon and an n-type dopant.

15. A semiconductor structure, comprising:

a base semiconductor portion surrounded by an isolation feature;

a vertical stack of nanostructures disposed over the base semiconductor portion;

inner spacer features interleaving the vertical stack of nanostructures;

a germanium cladding layer disposed around each of the vertical stack of nanostructures and on a top surface of the base semiconductor portion;

a semiconductor oxide layer disposed on the germanium cladding layer;

a gate dielectric layer disposed on the semiconductor oxide layer; and

a gate electrode layer disposed on the gate dielectric layer,

wherein the semiconductor oxide layer is in contact with the inner spacer features.

16. The semiconductor structure of claim 15 , wherein each of the vertical stack of nanostructures includes silicon and germanium.

17. The semiconductor structure of claim 15 , wherein the gate dielectric layer comprises hafnium oxide.

18. The semiconductor structure of claim 15 , wherein the semiconductor oxide layer comprises germanium oxide, silicon germanium oxide, or germanium-doped silicon oxide.

19. The semiconductor structure of claim 15 , further comprising:

a first source/drain feature and a second source/drain feature sandwiching the vertical stack of nanostructures,

wherein the first source/drain feature and the second source/drain feature comprise silicon germanium and a p-type dopant.

20. The semiconductor structure of claim 15 , wherein surfaces of the isolation feature are substantially free of the germanium cladding layer.