Voltage-glitch detection and protection circuit for secure memory devices

1. A circuit comprising:

a voltage-glitch-detection-block including:

a voltage-glitch-detector operable to detect a voltage-glitch in a supply voltage (VDD) and generate a voltage-glitch-detection-pulse (PULSE); and

a first latch having a set input coupled to the voltage-glitch-detector, the first latch operable to receive the PULSE and generate a first voltage-glitch-detection-pulse-latched (first PULSE_LATCHED) signal; and

a system reset block coupled the voltage-glitch-detector and the first latch to receive the PULSE and the first PULSE_LATCHED signal, and to generate a secure system reset signal that causes a number of on-chip-circuits in a chip including the circuit to be reset,

wherein the voltage-glitch-detector comprises:

a comparator having a first input coupled to VDD and a second input coupled to a reference voltage (V REF ) based on a predetermined set-point voltage (V GLITCH ), the comparator operable to compare VDD to V REF , and wherein the voltage-glitch-detector is operable to generate the PULSE when VDD<V REF ; and

a first voltage-glitch-isolation filter (GIF) through which the comparator is coupled to VDD to provide a filtered voltage (VDD RC ) to the comparator to isolate the comparator from a rapid decrease in VDD due to the voltage-glitch, and a second GIF through which the second input is coupled to V REF to isolate the comparator from a rapid change in V REF due to the voltage-glitch.

2. The circuit of claim 1 wherein the comparator is a current-comparator comprising a current-source operable to generate a voltage-glitch-current (I VOLTAGE-GLITCH ) based on V REF , and wherein the current-comparator is operable to compare I VOLTAGE-GLITCH to a current (I VDD ) from VDD applied to the first input to V REF , and to generate the PULSE when I VDD <I VOLTAGE-GLITCH .

3. The circuit of claim 2 wherein the first latch is a voltage-glitch-protected-latch comprising a third GIF and a sample and hold (S&H) circuit through which the voltage-glitch-protected-latch is coupled to VDD to provide a voltage (VDD RC S&H ) to power the voltage-glitch-protected-latch, and the first PULSE_LATCHED signal is coupled to the system reset block when VDD drops below V GLITCH .

4. The circuit of claim 1 wherein the voltage-glitch-detection-block further comprises reference voltage generator including a voltage-adder to generate V REF using a voltage-mirroring technique.

5. The circuit of claim 1 wherein the voltage-glitch-detection-block further comprises a reference voltage generator including a folding current-mirror with at least two-stages to generate V REF .

6. The circuit of claim 1 wherein the system reset block comprises a first level-detector coupled to receive the PULSE and the first PULSE_LATCHED signal, the first level-detector operable to generate the secure system reset signal.

7. A circuit comprising:

a voltage-glitch-detection-block including:

a voltage-glitch-detector operable to detect a voltage-glitch in a supply voltage (VDD) and generate a voltage-glitch-detection-pulse (PULSE); and

a first latch having a set input coupled to the voltage-glitch-detector, the first latch operable to receive the PULSE and generate a first voltage-glitch-detection-pulse-latched (first PULSE_LATCHED) signal; and

a system reset block coupled the voltage-glitch-detector and the first latch to receive the PULSE and the first PULSE_LATCHED signal, and to generate a secure system reset signal that causes a number of on-chip-circuits in a chip including the circuit to be reset,

wherein the system reset block comprises a first level-detector coupled to receive the PULSE and the first PULSE_LATCHED signal, the first level-detector operable to generate the secure system reset signal, and

wherein the system reset block further comprises a second level-detector coupled to VDD, and, through a logic gate, to a controller, wherein:

the second level-detector is operable to detect a drop in VDD below a predetermined minimum supply voltage (VDD MIN ) and generate a non-secure system reset signal;

the logic gate is operable to receive non-secure system reset signal from the second level-detector and the secure system reset signal from the first level-detector generate a system-reset-signal to the controller; and

the controller is operable to generate one or more global-reset-signals to reset the number of on-chip-circuits in the chip.

8. The circuit of claim 7 wherein the first latch further comprise a reset_b input coupled to an output of the logic gate.

9. The circuit of claim 7 wherein the voltage-glitch-detection-block further comprises a second latch having a set input coupled to the voltage-glitch-detector, the second latch operable to receive the PULSE from the voltage-glitch-detector, generate a second PULSE_LATCHED signal, and couple the second PULSE_LATCHED signal to design-for-testability logic in the circuit.

10. The circuit of claim 9 wherein second latch comprises a reset-b input coupled to receive the non-secure system reset signal from the second level-detector.

11. The circuit of claim 1 wherein the voltage-glitch-detector and first latch are operable to operate in a negative voltage domain during the voltage-glitch.

12. A system comprising:

an embedded non-volatile memory;

a circuit comprising:

a voltage-glitch-detection-block including:

a voltage-glitch-detector operable to detect a voltage-glitch in a supply voltage (VDD) and generate a voltage-glitch-detection-pulse (PULSE); and

a latch having a set input coupled to the voltage-glitch-detector, the

latch operable to receive the PULSE and generate a voltage-glitch-detection-pulse-latched (PULSE_LATCHED) signal; and

a system reset block coupled the voltage-glitch-detector and the latch to receive the PULSE and the PULSE_LATCHED signal, and to generate a secure system reset signal to reset the embedded non-volatile memory, the system reset block comprising:

a first level-detector coupled to receive the PULSE and the PULSE_LATCHED signal, the first level-detector operable to generate the secure system reset signal; and

a second level-detector coupled to VDD, and, through a logic gate, to a controller, wherein the second level-detector is operable to detect a drop in VDD below a predetermined minimum supply voltage (VDDMIN) and generate a non-secure system reset signal;

wherein the voltage-glitch-detector comprises a comparator having a first input coupled to VDD and a second input coupled to a reference voltage (V REF ) based on a predetermined setpoint voltage (V GLITCH ), the comparator operable to compare VDD to V REF , and wherein the voltage-glitch-detector is operable to generate the PULSE when VDD<V REF , and

wherein the latch is a voltage-glitch-protected-latch comprising a first voltage-glitch-isolation filter (GIF) and a sample and hold (S&H) circuit through which the voltage-glitch-protected-latch is coupled to VDD to provide a voltage (VDD RC S&H ) to power the voltage-glitch-protected-latch when VDD drops below V GLITCH .

13. The system of claim 12 wherein the comparator is a current-comparator comprising a current-source operable to generate a voltage-glitch-current (I VOLTAGE-GLITCH ) based on V REF , and wherein the current-comparator is operable to compare I VOLTAGE-GLITCH to a current (I VDD ) generated from VDD and to generate the PULSE when I VDD <I VOLTAGE-GLITCH .

14. The system of claim 13 wherein the voltage-glitch-detection-block further comprises a second GIF through which the comparator is coupled to VDD to provide a filtered voltage (VDD RC ) to the comparator to isolate the comparator from a rapid decrease in VDD due to the voltage-glitch, and a third GIF through which the second input is coupled to VREF to isolate the comparator from a rapid change in V REF due to the voltage-glitch.

15. The system of claim 12 wherein the system reset block comprises:

the logic gate is operable to receive non-secure system reset signal from the second level-detector and the secure system reset signal from the first level-detector generate a system-reset-signal to the controller; and

the controller is operable to generate the secure system reset signal to reset the embedded non-volatile memory.