Semiconductor memory device including at least one channel post with a first curved portion and a second curved portion having different curvatures and method for fabricating the same
A semiconductor memory device includes an electrode structure, a plurality of channel posts, and at least one gate separation layer. The electrode structure includes insulating interlayers and gate conductive layers which are alternately stacked. The channel posts are formed through the electrode structure. The gate separation layer is formed between the channel posts. The gate separation layer separates an uppermost gate conductive layer among the gate conductive layers. Each channel post among the channel posts adjacent to the gate separation layer has a gibbous moon shape in a planar view. The semiconductor memory device further includes a slit structure arranged at both sides of the gate separation layer. The slit structure is formed through the electrode structure. Each channel post among the channel posts adjacent to the slit structure has a gibbous moon shape in the planar view.
1. A semiconductor memory device comprising:
an electrode structure including insulating interlayers and gate conductive layers which are alternately stacked;
a plurality of channel posts formed to pass through the electrode structure; and
at least one gate separation layer arranged between the channel posts to separate an uppermost gate conductive layer among the gate conductive layers in the electrode structure,
wherein among the plurality of channel posts, channel posts adjacent to the gate separation layer have a first curved portion and a second curved portion having different curvatures in a planar view.
2. The semiconductor memory device of claim 1 , further comprising a slit structure arranged at both sides of the gate separation layer and formed to pass through the electrode structure,
wherein among the plurality of channel posts, channel posts adjacent to the slit structure have a gibbous moon shape in a planar view.
3. The semiconductor memory device of claim 1 , wherein the channel posts adjacent to the gate separation layer have a simple closed curve shape in a planar view that includes at least two curves having different curvatures.
4. The semiconductor memory device of claim 1 , wherein the channel posts adjacent to the gate separation layer comprise a first sector forming the first curved portion and a second sector forming the second curved portion.
5. The semiconductor memory device of claim 4 , wherein a first distance between a center point of a curve in the first sector and the center point of the first sector is shorter than a second distance between a center point of a curve in the second sector and the center point of the second sector, and wherein the curve in the second sector faces a sidewall of the gate separation layer.
6. The semiconductor memory device of claim 1 , wherein the gate separation layer comprises:
a trench formed in the electrode structure to separate the uppermost gate conductive layer; and
a separating insulation layer formed in the trench,
wherein the trench has a sidewall spaced apart from sidewalls of the channel posts adjacent to the gate separation layer.
7. The semiconductor memory device of claim 1 , wherein the gate separation layer comprises:
a trench formed in the electrode structure to separate the uppermost gate conductive layer; and
a separating insulation layer formed in the trench,
wherein the trench has a sidewall contacting sidewalls of the channel posts adjacent to the gate separation layer.
8. The semiconductor memory device of claim 1 , wherein the gate separation layer comprises:
a first trench formed in an uppermost insulating interlayer;
a spacer formed on a sidewall of the first trench;
a second trench extended from a bottom surface of the first trench and having a width narrower than a width of the first trench to separate the uppermost gate conductive layer; and
a separating insulation layer formed in the first trench and the second trench.
9. The semiconductor memory device of claim 8 , wherein the sidewall of the first trench is in contact with sidewalls of the channel posts adjacent to the gate separation layer, and wherein the second trench has a sidewall spaced apart from the sidewalls of the channel posts adjacent to the gate separation layer.
10. The semiconductor memory device of claim 1 , wherein among the plurality of channel posts, remaining channel posts not adjacent to the gate separation layer have a circular shape or an elliptical shape in a planar view.
11. The semiconductor memory device of claim 1 , wherein each of the plurality of channel posts comprises:
an opening formed to pass through the electrode structure;
a memory layer formed on a surface of the opening, the memory layer including a tunnel insulation layer, a charge-trapping layer, and a blocking layer which are sequentially stacked;
a channel layer formed on the memory layer;
a core layer formed on the channel layer to partially fill the opening; and
a capping layer formed on the core layer to fully fill the opening, the capping layer electrically connected with the channel layer.