Tool to create a reconfigurable interconnect framework
Embodiments are directed towards a method to create a reconfigurable interconnect framework in an integrated circuit. The method includes accessing a configuration template directed toward the reconfigurable interconnect framework, editing parameters of the configuration template, functionally combining the configuration template with a plurality of modules from an IP library to produce a register transfer level (RTL) circuit model, generating at least one automated test-bench function, and generating at least one logic synthesis script. Editing parameters of the configuration template includes confirming a first number of output ports of a reconfigurable stream switch and confirming a second number of input ports of the reconfigurable stream switch. Each output port and each input port has a respective architectural composition. The output port architectural composition is defined by a plurality of N data paths including A data outputs and B control outputs. The input port architectural composition is defined by a plurality of M data paths including A data inputs and B control inputs.
1. A non-transitory computer-readable medium storing a configuration template, which, when accessed by a computing device, is used by the computing device to generate a register transfer level (RTL) circuit model of a reconfigurable interconnect framework, the configuration template defining parameters including:
a first number of reconfigurable stream switch output ports of a stream switch of the reconfigurable interconnect framework, the stream switch being arranged to stream data tensors between logical modules, each output port having an output port architectural composition, wherein the output port architectural composition is defined by a plurality of N data paths of the stream switch, the plurality of N data paths including A data outputs and B control outputs, wherein N, A, and B are non-zero integers; and
a second number of reconfigurable stream switch input ports of the stream switch of the reconfigurable interconnect framework, each input port having an input port architectural composition, wherein the input port architectural composition is defined by a plurality of M data paths of the stream switch, the plurality of M data paths including A data inputs and B control inputs.
2. The non-transitory computer-readable medium of claim 1 wherein the configuration template is used by the computing device in combination with a database to generate the RTL circuit model.
3. The non-transitory computer-readable medium of claim 1 wherein the configuration template is used by the computing device to simulate circuitry.
4. The non-transitory computer-readable medium of claim 1 wherein the computing server combines the user-edited configuration template with a plurality of modules from a logic block (IP) library to produce the RTL circuit model.
5. The non-transitory computer-readable medium of claim 4 wherein integrated circuit fabrication machinery is coupled to the computing device and the computing device, based on the RTL circuit model, controls fabrication of a reconfigurable interconnect framework by the integrated circuit fabrication machinery.
6. The non-transitory computer-readable medium of claim 4 wherein the configuration template defines parameters of an accelerator framework and the RTL circuit model includes a model of an accelerator framework based on the configuration template.
7. The non-transitory computer-readable medium of claim 6 wherein the accelerator framework is a kernel accelerator framework.
8. The non-transitory computer-readable medium of claim 6 wherein the accelerator framework is a pre-processing accelerator framework.
9. The non-transitory computer-readable medium of claim 6 wherein the accelerator framework is a neural accelerator framework.
10. The non-transitory computer-readable medium of claim 6 wherein the accelerator framework is a convolutional accelerator framework.
11. The non-transitory computer-readable medium of claim 5 wherein the RTL circuit model is a model of a system on a chip (SoC) including the reconfigurable interconnect framework model.
12. The non-transitory computer-readable medium of claim 1 wherein the parameters defined by the configuration template include stream link configuration parameters of the stream switch, which define a reconfigurable stream switch output port associated with a stream link and one or more reconfigurable stream switch input ports associated with the stream link.
13. The non-transitory computer-readable medium of claim 12 wherein the stream link configuration parameters associated with the stream link define a number of communication paths of the stream link and a direction of each communication path.
14. A device, comprising:
control circuitry; and
a memory coupled to the control circuitry, the memory storing a configuration template defining parameters to generate a register transfer level (RTL) circuit model of a reconfigurable interconnect framework, the configuration template defining parameters including:
a first number of reconfigurable stream switch output ports of a stream switch of the reconfigurable interconnect framework, the stream switch being arranged to stream data tensors between logical modules, each output port having an output port architectural composition, wherein the output port architectural composition is defined by a plurality of N data paths of the stream switch, the plurality of N data paths including A data outputs and B control outputs, wherein N, A, and B are non-zero integers; and
a second number of reconfigurable stream switch input ports of the stream switch of the reconfigurable interconnect framework, each input port having an input port architectural composition, wherein the input port architectural composition is defined by a plurality of M data paths of the stream switch, the plurality of M data paths including A data inputs and B control inputs.
15. The device of claim 14 wherein the memory stores a database, and in operation, the databased is used in combination with the configuration template to generate the RTL circuit model.
16. The device of claim 14 wherein the configuration template defines parameters of an accelerator framework and the RTL circuit model includes a model of an accelerator framework based on the configuration template.
17. The device of claim 16 wherein the accelerator framework is a kernel accelerator framework.
18. The device of claim 16 wherein the accelerator framework is a pre-processing accelerator framework.
19. The device of claim 14 wherein the RTL circuit model is a model of a system on a chip (SoC) including the reconfigurable interconnect framework model.
20. The device of claim 14 wherein the parameters defined by the configuration template include stream link configuration parameters of the stream switch, which define a reconfigurable stream switch output port associated with a stream link and one or more reconfigurable stream switch input ports associated with the stream link.
21. The device of claim 16 , wherein the parameters defined by the configuration template include convolutional accelerator parameters of the accelerator framework.
22. The device of claim 16 , wherein the parameters defined by the configuration template include parameters of a set of control registers of the accelerator framework.
23. The non-transitory computer-readable medium of claim 4 wherein the plurality of modules from the logic block (IP) library include one or more convolutional accelerator models.
24. The non-transitory computer-readable medium of claim 4 wherein the plurality of modules from the logic block (IP) library include a model of a set of control registers.
25. The non-transitory computer-readable medium of claim 6 , wherein the parameters defined by the configuration template include a selected number of convolutional accelerators of the accelerator framework and memory parameters associated with one or more of the selected number of convolutional accelerators.
26. The device of claim 16 , wherein the parameters defined by the configuration template include a selected number of convolutional accelerators of the accelerator framework and memory parameters associated with one or more of the selected number of convolutional accelerators.