IP Library › Granted Patent US 11,675,947
Granted Patent B2
US 11,675,947 · App. 17/240,052 · Granted Jun 13, 2023

Multidimensional FPGA virtualization

Inventors: Bogdan Uscumlic (Les Ulis, FR); Yu-Chia Tseng (Massy, FR); Gopalasingham Aravinthan (Nozay, FR)
Assignee: Nokia Solutions and Networks Oy
G06F30/343G06F30/34G06F30/347G06F30/392
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Quick Facts
Patent No.
US 11,675,947
App. No.
17/240,052
Granted
Jun 13, 2023
Kind
B2
Abstract

A network device includes processing circuitry configured to: determine whether to initiate a temporal reconfiguration or a spatial reconfiguration of a partial reconfiguration slot on a programmable device, and initiate the temporal reconfiguration or the spatial reconfiguration of the partial reconfiguration slot in response to determining that the temporal reconfiguration or the spatial reconfiguration is to be initiated.

Claims (26)

1. A network device comprising:

processing circuitry configured to

determine whether to initiate a temporal reconfiguration or a spatial reconfiguration of a partial reconfiguration slot on a programmable device, and

initiate the temporal reconfiguration or the spatial reconfiguration of the partial reconfiguration slot in response to determining that the temporal reconfiguration or the spatial reconfiguration is to be initiated.

2. The network device of claim 1 , wherein

the partial reconfiguration slot includes a plurality of spatio-temporal slots configured to perform logical functions, and

the temporal reconfiguration includes switching from a first of the plurality of spatio-temporal slots to a second of the plurality of spatio-temporal slots.

3. The network device of claim 1 , wherein the spatial reconfiguration includes a physical reprogramming of the partial reconfiguration slot or a spatio-temporal slot within the partial reconfiguration slot.

4. The network device of claim 3 , wherein the physical reprogramming includes loading a bitstream onto the partial reconfiguration slot or the spatio-temporal slot.

5. The network device of claim 1 , further comprising:

the programmable device, wherein the programmable device includes a plurality of partial reconfiguration slots including the partial reconfiguration slot, and wherein

the processing circuitry is configured to load balance traffic between the plurality of partial reconfiguration slots.

6. The network device of claim 1 , further comprising:

the programmable device, wherein the programmable device includes a plurality of spatio-temporal slots nested in the partial reconfiguration slot.

7. The network device of claim 1 , wherein the programmable device is a field-programmable gate array (FPGA).

8. A method comprising:

determining whether to perform a temporal reconfiguration or a spatial reconfiguration of a partial reconfiguration slot on a programmable device; and

performing the temporal reconfiguration or the spatial reconfiguration of the partial reconfiguration slot in response to determining that the temporal reconfiguration or the spatial reconfiguration is to be initiated.

9. The method of claim 8 , wherein

the partial reconfiguration slot includes a plurality of spatio-temporal slots configured to perform logical functions, and

the performing the temporal reconfiguration includes switching from a first of the plurality of spatio-temporal slots to a second of the plurality of spatio-temporal slots.

10. The method of claim 8 , wherein the performing the spatial reconfiguration includes physically reprogramming the partial reconfiguration slot or a spatio-temporal slot within the partial reconfiguration slot.

11. The method of claim 10 , wherein the physically reprogramming includes loading a bitstream onto the partial reconfiguration slot or the spatio-temporal slot.

12. The method of claim 8 , wherein

the programmable device includes a plurality of partial reconfiguration slots including the partial reconfiguration slot, and

the method further includes load balancing traffic between the plurality of partial reconfiguration slots.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 26, 2021
From: USCUMLIC, BOGDAN; TSENG, YU-CHIA; ARAVINTHAN, GOPALASINGHAM
To: NOKIA BELL LABS FRANCE SASU
Reel/Frame 056042/0915 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 26, 2021
From: NOKIA BELL LABS FRANCE SASU
To: NOKIA SOLUTIONS AND NETWORKS OY
Reel/Frame 056042/0966 →
Continuity (1)
Related Publication 20220343046A1 · Oct 27, 2022
Cited By (1)
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