Lithography simulation method

1. A method of manufacturing a semiconductor device, the method comprising:

obtaining optical proximity correction (OPC) data by performing OPC to a circuit pattern using an wafer edge bias table;

manufacturing a photomask using the obtained OPC data; and

manufacturing a semiconductor device using the photomask,

wherein the wafer edge bias table comprises at least one selected from the group consisting of a scalar value corresponding to a target pattern of a given layout, the scalar value being dependent on a geometry feature of the target pattern, a location of the target pattern relative to the given layout, and a geometry feature of a neighboring pattern neighboring the target pattern.

2. The method of claim 1 , wherein the wafer edge bias table comprises the geometry feature of the neighboring pattern.

3. The method of claim 2 , wherein the geometry feature of the neighboring pattern neighboring the target pattern comprises at least one selected from the group consisting of a line width of an edge of the neighboring pattern, a space width of the edge of the neighboring pattern, a length of an edge of the neighboring pattern, a density of edges in the neighboring pattern, and a corner-to-corner distance in the neighboring pattern.

4. The method of claim 2 , wherein the neighboring pattern comprises a pattern of a nearest neighbor of the target pattern.

5. The method of claim 2 , wherein the neighboring pattern comprises patterns of k-nearest neighbors of the target pattern, wherein k is a natural number.

6. The method of claim 1 , wherein the wafer edge bias table comprises the scalar value corresponding to each pattern of the given layout.

7. The method of claim 6 , wherein the scalar value is dependent on a weighted average of biases of k-nearest neighbors of the target pattern, wherein k is a natural number.

8. The method of claim 7 , wherein the k-nearest neighbors are determined as a function of a distance relative to an edge of the target pattern.

9. The method of claim 8 , wherein a weight of a given neighbor depends on a distance of the given neighbor relative to the edge of the target pattern.

10. The method of claim 6 , wherein the geometry feature of the target pattern comprises at least one selected from the group consisting of a length of an edge of the target pattern, an orientation of the target pattern, and an orientation of the edge relative to the target pattern.

11. The method of claim 1 , wherein the wafer edge bias table comprises the location of the target pattern relative to the given layout.

12. The method of claim 1 , wherein the wafer edge bias table is generated by:

(i) forming a test mask in accordance with a test layout;

(ii) printing a test wafer pattern by optical lithography using the test mask;

(iii) measuring the test wafer pattern;

(iv) simulating a pattern using an initial wafer edge bias table for the test layout;

(v) obtaining a difference between the simulated pattern and the measured test wafer pattern; and

repeating (i)-(v) until the difference between the simulated pattern and the measured test wafer pattern is smaller than a threshold or a limit for a number of iterations has been reached.

13. The method of claim 12 , wherein the optical lithography is extreme ultra violet lithography.

14. A lithography simulator comprising:

a non-transitory computer-readable memory storing a program; and

a processor operatively coupled with the memory, wherein:

the program, when executed by the processor, causes the processor to perform an optical proximity correction to a circuit pattern including a target pattern using a wafer edge bias table,

the wafer edge bias table comprises a scalar value corresponding to each pattern of the given layout,

the scalar value is dependent on a geometry feature of a pattern, and

the geometry feature of the target pattern comprises at least one selected from the group consisting of a length of an edge of the target pattern, an orientation of the target pattern, and an orientation of the edge relative to the target pattern.

15. The lithography simulator of claim 14 , wherein the scalar value is dependent on a weighted average of biases of k-nearest neighbors of the target pattern, wherein k is a natural number.

16. The lithography simulator of claim 15 , wherein the k-nearest neighbors are determined as a function of a distance relative to an edge of the target pattern.

17. The lithography simulator of claim 16 , wherein a weight of a given neighbor depends on a distance of the given neighbor relative to the edge of the target pattern.

18. The lithography simulator of claim 14 , wherein the geometry feature of the target pattern comprises an orientation of the target pattern.

19. A lithography simulator comprising:

a non-transitory computer-readable memory storing a program; and

a processor operatively coupled with the memory,

wherein the program, when executed by the processor, causes the processor to perform an optical proximity correction to a circuit pattern using a wafer edge bias table,

the wafer edge bias table comprises a geometry feature of a neighboring pattern neighboring a target pattern, and

the geometry feature of the neighboring pattern neighboring the target pattern comprises at least one selected from the group consisting of a line width of an edge of the neighboring pattern, a space width of the edge of the neighboring pattern, a length of an edge of the neighboring pattern, a density of edges in the neighboring pattern, and a corner-to-corner distance in the neighboring pattern.

20. The lithography simulator of claim 19 , wherein the geometry feature of the neighboring pattern neighboring the target pattern comprises at least one selected from the group consisting of a density of edges in the neighboring pattern, and a corner-to-corner distance in the neighboring pattern.