Display device and operating method thereof
A display device that achieves both high-accuracy sensing by a touch sensor unit and smooth input using the touch sensor unit is provided. The display device includes a display unit and the touch sensor unit. The touch sensor unit performs touch sensing operation at a different timing from display image rewriting by the display unit, whereby the high-accuracy sensing can be achieved. The display unit has a function of rewriting a display image only in a region that needs to be rewritten. In the case where the entire display region is not necessarily rewritten, the time for the sensing operation by the touch sensor unit can be lengthened, whereby the smooth input can be achieved.
1. A display device comprising:
a plurality of pixels, each of the plurality of pixels comprising a light-emitting element;
a source driver;
a demultiplexer; and
a plurality of gate drivers sandwiching a pixel array, one of the plurality of gate drivers comprising a shift register, the shift register comprising:
a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor; and
a first wiring, a second wiring, a third wiring, and a fourth wiring,
wherein one of a source and a drain of the first transistor is directly connected to one of a source and a drain of the sixth transistor,
wherein the one of the source and the drain of the first transistor is directly connected to the first wiring,
wherein the one of the source and the drain of the sixth transistor is electrically connected to the first wiring,
wherein one of a source and a drain of the second transistor is electrically connected to the other of the source and the drain of the first transistor, a first output terminal, and a second output terminal,
wherein the other of the source and the drain of the second transistor is electrically connected to the third wiring,
wherein a gate of the second transistor is electrically connected to one of a source and a drain of the third transistor and one electrode of a first capacitor,
wherein a gate of the third transistor is electrically connected to the second wiring,
wherein the other of the source and the drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor,
wherein a gate of the fourth transistor is directly connected to a gate of the eighth transistor,
wherein the gate of the fourth transistor is electrically connected to one of a source and a drain of the seventh transistor and one electrode of a second capacitor,
wherein a gate of the fifth transistor and a gate of the sixth transistor are electrically connected to the fourth wiring, and
wherein neither of a source and a drain of the fifth transistor is directly connected to the one of the source and the drain of the seventh transistor and the other of the source and the drain of the seventh transistor.
2. A display device comprising:
a plurality of pixels, each of the plurality of pixels comprising a light-emitting element;
a source driver;
a demultiplexer comprising a transistor comprising silicon in a channel formation region and electrically connected to the source driver; and
a plurality of gate drivers sandwiching a pixel array, one of the plurality of gate drivers comprising a shift register, the shift register comprising:
a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor; and
a first wiring, a second wiring, a third wiring, and a fourth wiring,
wherein one of a source and a drain of the first transistor is directly connected to one of a source and a drain of the sixth transistor,
wherein the one of the source and the drain of the first transistor is directly connected to the first wiring,
wherein the one of the source and the drain of the sixth transistor is electrically connected to the first wiring,
wherein one of a source and a drain of the second transistor is electrically connected to the other of the source and the drain of the first transistor, a first output terminal, and a second output terminal,
wherein the other of the source and the drain of the second transistor is electrically connected to the third wiring,
wherein a gate of the second transistor is electrically connected to one of a source and a drain of the third transistor and one electrode of a first capacitor,
wherein a gate of the third transistor is electrically connected to the second wiring,
wherein the other of the source and the drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor,
wherein a gate of the fourth transistor is directly connected to a gate of the eighth transistor,
wherein the gate of the fourth transistor is electrically connected to one of a source and a drain of the seventh transistor and one electrode of a second capacitor,
wherein a gate of the fifth transistor and a gate of the sixth transistor are electrically connected to the fourth wiring, and
wherein neither of a source and a drain of the fifth transistor is directly connected to the one of the source and the drain of the seventh transistor and the other of the source and the drain of the seventh transistor.
3. A display device comprising:
a plurality of pixels, each of the plurality of pixels comprising a light-emitting element;
a source driver;
a demultiplexer; and
a plurality of gate drivers sandwiching a pixel array, one of the plurality of gate drivers comprising a shift register, the shift register comprising:
a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, and a ninth transistor; and
a first wiring and a second wiring,
wherein one of a source and a drain of the first transistor is electrically connected to the second wiring,
wherein the other of the source and the drain of the first transistor is directly connected to one of a source and a drain of the second transistor,
wherein the other of the source and the drain of the first transistor is electrically connected to a first output terminal and a second output terminal,
wherein the other of the source and the drain of the second transistor is electrically connected to one of a source and a drain of the third transistor and one electrode of a first capacitor,
wherein a gate of the first transistor is electrically connected to one electrode of a second capacitor and one of a source and a drain of the fourth transistor,
wherein a gate of the fourth transistor is electrically connected to a third wiring and one of a source and a drain of the sixth transistor,
wherein the other of the source and the drain of the second transistor, the one of the source and the drain of the third transistor, and the one electrode of the first capacitor are electrically connected to the first wiring and one of a source and a drain of the fifth transistor,
wherein the other of the source and the drain of the sixth transistor is electrically connected to a gate of the fifth transistor, a gate of the seventh transistor, and one of a source and a drain of the eighth transistor, and
wherein one of a source and a drain of the seventh transistor is electrically connected to one of a source and a drain of the ninth transistor.
4. The display device according to claim 3 ,
wherein the demultiplexer comprises a transistor comprising silicon in a channel formation region, and
wherein the demultiplexer is electrically connected to the source driver.