Semiconductor device and method for fabricating the same
A method for fabricating a semiconductor device includes: preparing a substrate; forming an isolation layer defining an active region in the substrate; forming a first insulation structure over the substrate, the first insulation structure defining a line-type opening that exposes the isolation layer and the active region; forming a plug pad through a Selective Epitaxial Growth (SEG) process over the exposed active regions; forming a second insulation structure inside the line-type opening, the second insulation structure defining a contact hole landing on the plug pad; and filling the contact hole with a contact plug.
1. A semiconductor device, comprising:
a semiconductor substrate including an active region and an isolation layer;
a plurality of bit lines over the semiconductor substrate;
a line-type opening that is formed between the bit lines and includes a recess which exposes the active region and the isolation layer;
a silicon-containing pad selectively grown on the exposed active region;
a plug isolation structure that is formed inside the line-type opening to expose the silicon-containing pad and defines a contact hole having a smaller landing area than a surface area of an upper portion of the silicon-containing pad; and
a silicon-containing plug formed on the silicon-containing pad inside the contact hole,
wherein the silicon-containing pad comprising:
a central portion formed on the active region; and
a side extended portion that laterally grows up from the central portion to extend over the isolation layer.
2. The semiconductor device of claim 1 , wherein the silicon-containing pad includes a selective epitaxial layer.
3. The semiconductor device of claim 1 , wherein the silicon-containing pad includes a SEG-Si, SEG-SiGe, SEG-SiC or SEG-SiP.
4. The semiconductor device of claim 1 , wherein the plug isolation structure includes:
a spacer that is formed on both side walls of the line-type opening; and
a plug isolation layer that is formed inside the line-type opening where the spacer is formed, and
the contact hole is defined by being self-aligned to the plug isolation layer and the spacer.
5. The semiconductor device of claim 1 , further comprising:
a word line buried in the semiconductor substrate;
first and second source/drain regions that are formed in the semiconductor substrate on both sides of the word line;
a bit line contact plug formed on the first source/drain region; and
a bit line formed on the bit line contact plug,
wherein the silicon-containing pad is coupled to the second source/drain region.
6. The semiconductor device of claim 1 , further comprising:
an ohmic contact layer on the silicon-containing plug;
a metal plug on the ohmic contact layer; and
a memory element formed over the metal plug.
7. The semiconductor device of claim 6 , further comprising:
an interface doping layer positioned between the ohmic contact layer and the silicon-containing plug.
8. The semiconductor device of claim 7 , wherein the interface doping layer and the silicon-containing plug include the same dopant.
9. The semiconductor device of claim 1 , wherein the silicon-containing plug includes poly silicon.