Integrated circuit device, system and method
An integrated circuit (IC) device includes a substrate having opposite first and second sides, an active region over the first side of the substrate, a first conductive pattern over the active region, and a second conductive pattern under the second side of the substrate. The active region includes a first portion and a second portion. The first conductive pattern is electrically coupled to the first portion and the second portion of the active region. The second conductive pattern is electrically coupled to the first portion and the second portion of the active region.
1. An integrated circuit (IC) device, comprising:
a substrate having opposite first and second sides;
an active region over the first side of the substrate, the active region comprising a first portion and a second portion;
a first conductive pattern over the active region, and electrically coupling the first portion to the second portion of the active region; and
a second conductive pattern under the second side of the substrate, and electrically coupling the first portion to the second portion of the active region.
2. The IC device of claim 1 , further comprising:
a first through via structure extending from the second side, through the substrate, to the first side in electrical contact with the first portion of the active region; and
a second through via structure extending from the second side, through the substrate, to the first side in electrical contact with the second portion of the active region,
wherein the second conductive pattern is electrically coupled to the first through via structure and the second through via structure.
3. The IC device of claim 2 , further comprising:
a first contact structure over and in electrical contact with the first portion of the active region, the first contact structure electrically coupled to the first conductive pattern; and
a second contact structure over and in electrical contact with the second portion of the active region, the second contact structure electrically coupled to the first conductive pattern.
4. The IC device of claim 3 , wherein at least one of
the first contact structure and the first through via structure are in direct contact with corresponding opposite surfaces of the first portion of the active region, or
the second contact structure and the second through via structure are in direct contact with corresponding opposite surfaces of the second portion of the active region.
5. The IC device of claim 3 , wherein
along a thickness direction of the substrate from the first side to the second side,
the first conductive pattern, the first contact structure, the first portion of the active region, the first through via structure, and the second conductive pattern overlap one another, and
the first conductive pattern, the second contact structure, the second portion of the active region, the second through via structure, and the second conductive pattern overlap one another.
6. The IC device of claim 1 , wherein
the first conductive pattern is in a metal-zero layer, and
the second conductive pattern is in a back side metal-zero layer.
7. The IC device of claim 1 , further comprising:
a dummy gate between the first portion and the second portion of the active region.
8. The IC device of claim 7 , wherein
the dummy gate includes a dielectric material.
9. The IC device of claim 1 , further comprising:
a plurality of gates extending across the active region, and configuring together with the active region a plurality of transistors,
wherein
the plurality of transistors comprises
a first transistor having a source/drain being the first portion of the active region, and
a second transistor having a source/drain being the second portion of the active region, and
the first transistor and the second transistor configure a differential pair of transistors.
10. The IC device of claim 1 , further comprising:
a plurality of gates extending across the active region, and configuring together with the active region a plurality of transistors,
wherein
the plurality of transistors comprises
a first transistor having a source/drain being the first portion of the active region, and
a second transistor having a source/drain being the second portion of the active region, and
the plurality of transistors are coupled into a daisy chain arrangement of a serializer/deserializer (SERDES) device.
11. A system, comprising:
a processor configured to generate an integrated circuit (IC) layout useable for manufacturing an IC device, the IC layout comprising:
an active region;
a plurality of gate regions extending across the active region, the plurality of gate regions comprising a first gate region and a second gate region;
a first contact region over the active region, and adjacent to the first gate region;
a second contact region over the active region, and adjacent to the second gate region;
a first via over the first contact region;
a second via over the second contact region;
a first conductive pattern over the first via and the second via;
a first through via under the first contact region and the active region;
a second through via under the second contact region and the active region; and
a second conductive pattern under the first through via and the second through via,
wherein
the first conductive pattern, the first via, the first contact region, the first through via, and the second conductive pattern overlap one another, and
the first conductive pattern, the second via, the second contact region, the second through via, and the second conductive pattern overlap one another.
12. The system of claim 11 , wherein
the processor is configured to generate or place, on the IC layout,
the first conductive pattern in a metal-zero layer, and
the second conductive pattern in a back side metal-zero layer.
13. The system of claim 11 , wherein
the processor is configured to generate or place, on the IC layout,
the second conductive pattern comprising a power supply voltage rail.
14. The system of claim 11 , wherein
the processor is configured to generate or place, on the IC layout,
the first conductive pattern with a width smaller than a width of the second conductive pattern.
15. The system of claim 11 , wherein
the processor is configured to generate or place, on the IC layout, at least one of
the first contact region with an area smaller than an area of the first through via, or
the second contact region with an area smaller than an area of the second through via.
16. The system of claim 11 , wherein
the processor is configured to generate or place, on the IC layout,
the plurality of gate regions further comprising a dummy gate region arranged
between the first gate region and the second gate region, and
between the first contact region and the second contact region.
17. The system of claim 16 , wherein
the processor is configured to generate or place, on the IC layout,
the dummy gate region immediately adjacent to the first gate region and the second gate region.
18. A method, comprising:
forming a first transistor and a second transistor over a first side of a substrate, the substrate having a second side opposite the first side;
forming, in a first metal layer over the first side of the substrate, a first conductive pattern electrically coupling a first source/drain of the first transistor to a second source/drain of the second transistor; and
forming, in a second metal layer under the second side of the substrate, a second conductive pattern electrically coupling the first source/drain of the first transistor to the second source/drain of the second transistor.
19. The method of claim 18 , further comprising:
removing a conductive material from a third gate arranged between a first gate of the first transistor and a second gate of the second transistor.
20. The method of claim 19 , further comprising:
after said removing, filling a dielectric material into the third gate.