Stacked transistors having device strata with different channel widths
Disclosed herein are stacked transistors having device strata with different channel widths, as well as related methods and devices. In some embodiments, an integrated circuit structure may include stacked strata of transistors, wherein different channel materials of different strata have different widths.
1. An integrated circuit (IC) structure, comprising:
a first device stratum including a first channel material, wherein the first channel material includes a wire;
a second device stratum including a second channel material, wherein the second channel material is above and aligned with the first channel material, and the second channel material includes a fin;
a first gate metal at least partially surrounding the first channel material; and
a second gate metal at least partially surrounding the second channel material;
wherein a width of the first channel material is different from a width of the second channel material and the first gate metal has a different material composition than the second gate metal.
2. The IC structure of claim 1 , wherein the width of the first channel material is less than the width of the second channel material.
3. The IC structure of claim 1 , wherein the width of the first channel material is greater than the width of the second channel material.
4. The IC structure of claim 1 , wherein the first device stratum is between a silicon-on-insulator structure and the second device stratum.
5. The IC structure of claim 1 , wherein the width of the first channel material is between 10 nanometers and 30 nanometers.
6. The IC structure of claim 5 , wherein the width of the second channel material is between 5 nanometers and 10 nanometers.
7. An integrated circuit (IC) die, comprising:
a first device stratum including a first channel material, wherein the first channel material has a first width, and the first channel material includes a wire;
a second device stratum including a second channel material, wherein the second channel material has a second width different from the first width, the second channel material is above the first channel material and the second channel material includes a fin;
a first gate metal at least partially surrounding the first channel material; and
a second gate metal at least partially surrounding the second channel material;
wherein the first channel material has a different material composition than the second channel material, and the first gate metal has a different material composition than the second gate metal.
8. The IC die of claim 7 , wherein the first width is less than the second width.
9. The IC die of claim 7 , wherein the first channel material includes silicon or germanium.
10. The IC die of claim 7 , wherein the second channel material includes a III-V material.
11. The IC die of claim 7 , wherein the first channel material is a channel of a p-type metal oxide semiconductor (PMOS) transistor.
12. The IC die of claim 7 , wherein the second channel material is a channel of an n-type metal oxide semiconductor (NMOS) transistor.
13. The IC die of claim 7 , further comprising:
a plurality of conductive contacts at an outer face of the IC die, wherein at least some of the conductive contacts are in electrical contact with the first device stratum or the second device stratum.
14. A computing device, comprising:
a circuit board; and
an integrated circuit (IC) package coupled to the circuit board, wherein the IC package includes a package substrate and an IC die coupled to the package substrate, and the IC die includes stacked strata of transistors, wherein different channel materials of different strata have different widths and are at least partially enclosed by different gate metals, the stacked strata of transistors comprising:
first device stratum including a first channel material, wherein the first channel material includes a wire; and
a second device stratum including a second channel material, wherein the second channel material is above the first channel material, and the second channel material includes a fin.
15. The computing device of claim 14 , wherein the first device stratum includes a plurality of semiconductor wires.
16. The computing device of claim 15 , wherein the plurality of semiconductor wires include a III-V material.
17. The computing device of claim 14 , wherein the fin includes silicon or germanium, and the fin has a width that is less than a width of the wire.
18. The computing device of claim 14 , wherein the IC die is coupled to the package substrate by solder balls.
19. The computing device of claim 14 , wherein the computing device is a tablet computing device, a handheld computing device, a smart phone, a wearable computing device, or a server.