IP Library › Granted Patent US 11,676,975
Granted Patent B2
US 11,676,975 · App. 16/104,397 · Granted Jun 13, 2023

Semiconductor device

Inventors: Shunpei Yamazaki (Tokyo, JP); Jun Koyama (Kanagawa, JP); Kiyoshi Kato (Kanagawa, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
H01L27/1255H01L21/84H01L27/108H01L27/10805H01L27/10873H01L27/11H01L27/1108H01L27/1156H01L27/11517H01L27/11521H01L27/11803H01L27/1225H01L29/24H01L29/7869G11C16/0433G11C16/26
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Quick Facts
Patent No.
US 11,676,975
App. No.
16/104,397
Granted
Jun 13, 2023
Kind
B2
Abstract

An object of the present invention is to provide a semiconductor device having a novel structure in which in a data storing time, stored data can be stored even when power is not supplied, and there is no limitation on the number of writing. A semiconductor device includes a first transistor including a first source electrode and a first drain electrode; a first channel formation region for which an oxide semiconductor material is used and to which the first source electrode and the first drain electrode are electrically connected; a first gate insulating layer over the first channel formation region; and a first gate electrode over the first gate insulating layer. One of the first source electrode and the first drain electrode of the first transistor and one electrode of a capacitor are electrically connected to each other.

Claims (53)

1. A semiconductor device comprising:

a transistor comprising:

an oxide semiconductor layer;

a first conductive layer over the oxide semiconductor layer;

a second conductive layer over the first conductive layer;

a gate electrode; and

a gate insulating layer between the oxide semiconductor layer and the gate electrode,

wherein a side surface of the first conductive layer comprises a first region,

wherein the gate electrode and the oxide semiconductor layer overlap with each other,

wherein the first conductive layer comprises copper,

wherein the first region comprises copper and oxygen,

wherein the second conductive layer is formed using a metal different from that of the first conductive layer,

wherein the first conductive layer is in contact with the oxide semiconductor layer, and

wherein the first region is over the oxide semiconductor layer.

2. The semiconductor device according to claim 1 , wherein the oxide semiconductor layer is an intrinsic or substantially intrinsic oxide semiconductor layer.

3. The semiconductor device according to claim 1 , wherein the oxide semiconductor layer comprises indium, gallium, and zinc.

4. A semiconductor device comprising:

a transistor comprising:

an oxide semiconductor layer;

a first conductive layer over the oxide semiconductor layer;

a second conductive layer over the first conductive layer;

a gate electrode; and

a gate insulating layer between the oxide semiconductor layer and the gate electrode,

wherein a side surface of the first conductive layer comprises a first region,

wherein the gate electrode and the oxide semiconductor layer overlap with each other,

wherein the first conductive layer comprises copper,

wherein the first region comprises copper and oxygen,

wherein the second conductive layer is formed using a metal different from that of the first conductive layer,

wherein a first part of a top surface of the gate electrode is at a level lower than a second part of the top surface of the gate electrode,

wherein the first part of the top surface of the gate electrode and a channel formation region of the oxide semiconductor layer overlap each other,

wherein the first conductive layer is in contact with the oxide semiconductor layer, and

wherein the first region is over the oxide semiconductor layer.

5. The semiconductor device according to claim 4 , wherein the oxide semiconductor layer is an intrinsic or substantially intrinsic oxide semiconductor layer.

6. The semiconductor device according to claim 4 , wherein the oxide semiconductor layer comprises indium, gallium, and zinc.

7. A semiconductor device comprising:

a transistor comprising:

an oxide semiconductor layer;

a first conductive layer over the oxide semiconductor layer;

a second conductive layer over the first conductive layer;

a gate electrode; and

a gate insulating layer between the oxide semiconductor layer and the gate electrode,

wherein an edge portion of the first conductive layer has a first tapered shape,

wherein a first region is formed in part of the first conductive layer,

wherein the first conductive layer comprises copper,

wherein the first region comprises copper and oxygen,

wherein the second conductive layer is formed using a metal different from that of the first conductive layer,

wherein the first conductive layer is in contact with the oxide semiconductor layer, and

wherein the first region is over the oxide semiconductor layer.

8. The semiconductor device according to claim 7 , wherein the oxide semiconductor layer is an intrinsic or substantially intrinsic oxide semiconductor layer.

9. The semiconductor device according to claim 7 , wherein the oxide semiconductor layer comprises indium, gallium, and zinc.

10. The semiconductor device according to claim 1 , wherein the first region is between the first conductive layer and the gate insulating layer.

11. The semiconductor device according to claim 4 , wherein the first region is between the first conductive layer and the gate insulating layer.

12. The semiconductor device according to claim 7 , wherein the first region is between the first conductive layer and the gate insulating layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 21, 2018
From: YAMAZAKI, SHUNPEI; KOYAMA, JUN; KATO, KIYOSHI
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 046642/0704 →
Priority Claims (1)
JP 2009-296201 · Dec 25, 2009 · national
Continuity (4)
Continuation 14730436 · Jun 4, 2015
Continuation 13928425 · Jun 27, 2013
Division 12976582 · Dec 22, 2010
Related Publication 20190006397A1 · Jan 3, 2019