Driver circuit and method of operating the same

1. A circuit comprising:

a power supply voltage node configured to have a power supply voltage level;

a protection circuit comprising a voltage divider coupled to a detection circuit, the detection circuit configured to generate a first signal having first and second logical voltage levels based on the power supply voltage level; and

a gate driver comprising:

a first n-type high electron mobility transistor (HEMT) coupled between the power supply voltage node and a first node, the first n-type HEMT comprising a first gate configured to receive the first signal;

a second n-type HEMT coupled between the first node and a power supply reference node, the second n-type HEMT comprising a second gate configured to receive a second signal; and

a direct-coupled FET logic (DCFL) circuit coupled between the first node and an output terminal,

wherein the DCFL circuit is configured to generate a third signal at the output terminal based on the second signal when the first signal has the first logical voltage level, and as a direct current (DC) voltage level when the first signal has the second logical voltage level.

2. The circuit of claim 1 , wherein

the voltage divider is configured to generate a first voltage level from the power supply voltage level; and

the detection circuit comprises:

a third n-type HEMT configured to generate a second voltage level responsive to the first voltage level; and

a fourth n-type HEMT configured to generate the first signal responsive to the second voltage level.

3. The circuit of claim 2 , wherein

each of the third and fourth n-type HEMTs is an enhancement-mode HEMT, and

the protection circuit further comprises:

a first depletion-mode n-type HEMT configured as a load transistor coupled between the power supply voltage node and the third n-type HEMT; and

a second depletion-mode n-type HEMT configured as a load transistor coupled between the power supply voltage node and the fourth n-type HEMT.

4. The circuit of claim 1 , wherein the gate driver further comprises a buffer amplifier coupled between the DCFL circuit and the output terminal.

5. The circuit of claim 1 , wherein the gate driver further comprises a bootstrap circuit coupled to the DCFL circuit and between the power supply voltage node and the output terminal.

6. The circuit of claim 1 , wherein

each of the first and second n-type HEMTs is an enhancement-mode HEMT, and

the gate driver further comprises a depletion-mode n-type HEMT configured as a load transistor coupled between the power supply voltage node and the first n-type HEMT.

7. The circuit of claim 1 , wherein each of the first and second n-type HEMTs comprises gallium nitride (GaN).

8. An integrated circuit (IC) comprising:

a protection circuit coupled to a first power supply voltage node, the protection circuit configured to generate a first signal based on a first power supply voltage level on the first power supply voltage node;

a gate driver comprising:

a first n-type high electron mobility transistor (HEMT) coupled between the first power supply voltage node and a first node, the first n-type HEMT comprising a first gate configured to receive the first signal;

a second n-type HEMT coupled between the first node and a power supply reference node, the second n-type HEMT comprising a second gate configured to receive a second signal; and

a direct-coupled FET logic (DCFL) circuit coupled to the first node and configured to generate a third signal; and

a switching device coupled to a second power supply voltage node configured to have a second power supply voltage level greater than the first power supply voltage level, the switching device comprising a third gate configured to receive the third signal,

wherein the protection circuit and the gate driver are configured to

control the switching device based on the second signal when the first power supply voltage level is equal to or greater than a threshold voltage level, and

switch off the switching device when the first power supply voltage level is less than the threshold voltage level.

9. The IC of claim 8 , wherein the first power supply voltage node is configured to receive the first power supply voltage level from a battery.

10. The IC of claim 8 , further comprising a pulse width modulation (PWM) circuit configured to generate the second signal.

11. The IC of claim 8 , wherein the gate driver further comprises:

a buffer amplifier coupled between the DCFL circuit and the switching device; and

a bootstrap circuit coupled to the DCFL circuit and between the power supply voltage node and the switching device.

12. The IC of claim 8 , further comprising a voltage conversion sub-circuit coupled between the second power supply voltage node and the switching device or between the switching device and the power supply reference node.

13. The IC of claim 8 , wherein

the gate driver is positioned adjacent to the protection circuit, and

the switching device is positioned adjacent to the gate driver.

14. The IC of claim 8 , wherein each of the first and second n-type HEMTs, the DCFL circuit, and the switching device comprises an enhancement-mode n-type HEMT comprising gallium nitride (GaN).

15. A method of operating a driver circuit, the method comprising:

outputting a first signal from a detection circuit of a protection circuit, the first signal having first and second logical voltage levels in response to a first power supply voltage level received at a voltage divider of the protection circuit coupled to the detection circuit;

receiving the first signal at a first n-type high electron mobility transistor (HEMT) of a gate driver;

receiving a second signal at a second n-type HEMT of the gate driver, the second n-type HEMT being arranged in series with the first n-type HEMT; and

using a direct-coupled FET logic (DCFL) circuit coupled to the first and second n-type HEMTs to output a third signal from the gate driver, wherein

the third signal is based on the second signal in response to the first signal having the first logical voltage level, and

the third signal has a direct current (DC) voltage level in response to the first signal having the second logical voltage level.

16. The method of claim 15 , wherein the protection circuit receives the first power supply voltage level from a battery.

17. The method of claim 15 , wherein the receiving the second signal at the second n-type HEMT of the gate driver comprises receiving a pulse width modulation (PWM) signal.

18. The method of claim 15 , further comprising

receiving the third signal at a high-voltage circuit configured to receive a second power supply voltage level greater than the first power supply voltage level;

using a switching device of the high-voltage circuit to perform a switching operation in response to the third signal being based on the second signal; and

using the switching device to perform a lockout operation in response to the third signal having the DC voltage level.

19. The method of claim 18 , wherein the receiving the third signal at the high-voltage circuit comprises the high-voltage circuit being some or all of a high-voltage portion of an IC chip that comprises the driver circuit adjacent to the high-voltage circuit.

20. The method of claim 18 , wherein the using the switching device to perform the switching and lockout operations comprises using an n-type HEMT comprising gallium nitride (GaN).