IP Library › Granted Patent US 11,677,497
Granted Patent B2
US 11,677,497 · App. 17/303,223 · Granted Jun 13, 2023

Apparatus and method of transmission using HARQ in communication or broadcasting system

Inventors: Hongsil Jeong (Suwon-si, KR); Kyungjoong Kim (Suwon-si, KR); Seho Myung (Seoul, KR)
Assignee: Samsung Electronics Co., Ltd.
H04L1/0058H03M13/116H03M13/1148H03M13/1185H03M13/616H03M13/6306H03M13/6393H04L1/0041H04L1/0045H04L1/0057H04L1/0067H04L1/1819H04L1/0003H04L1/0009H04L1/0071
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Quick Facts
Patent No.
US 11,677,497
App. No.
17/303,223
Granted
Jun 13, 2023
Kind
B2
Abstract

The present disclosure relates to a pre-5 th -Generation (5G) or 5G communication system to be provided for supporting higher data rates Beyond 4 th -Generation (4G) communication system such as Long Term Evolution (LTE). The present disclosure discloses a method for effective retransmission when HARQ is applied to data encoded with a low density parity check (LDCP) code. A data transmission method of the transmitter may include: initially transmitting data encoded with an LDPC code to a receiver; receiving a negative acknowledgement (NACK) from the receiver; determining retransmission related information for data retransmission; and retransmitting, in response to the NACK, LDPC-encoded data based on the retransmission related information.

Claims (76)

1. A method performed by a transmitter in a communication system, the method comprising:

identifying input bits to be transmitted;

identifying a code block based on the input bits;

identifying Z, a size of an identity matrix or a cyclically shifted matrix of the identity matrix;

identifying a parity check matrix for a low density parity check (LDPC) encoding based on the Z;

encoding the code block by the LDPC encoding based on the parity-check matrix and the Z;

identifying a redundancy version (RV) index;

generating a bit sequence by a rate matching on the encoded code block based on a bit position;

modulating the bit sequence; and

transmitting the modulated bit sequence,

wherein a part of the code block is not included in the encoded code block, and

the bit position is determined based on the RV index and a multiple of the Z.

2. The method of claim 1 ,

wherein a length of the part of the code block is 2×Z.

3. The method of claim 1 ,

wherein the part of the code block is not transmitted for an initial transmission and any re-transmission.

4. The method of claim 1 ,

wherein the rate matching comprises reordering the encoded code block from the bit position.

5. The method of claim 1 , wherein the encoded code block includes of cyclic redundancy check (CRC) bits.

6. A method performed by a receiver in a communication system, the method comprising:

receiving a signal;

demodulating the received signal to identify a demodulated bit sequence;

identifying Z, a size of an identity matrix or a cyclically shifted matrix of the identity matrix;

identifying a parity check matrix for a low density parity check (LDPC) decoding based on the Z;

identifying a redundancy version (RV) index; and

identifying a code block by the LDPC decoding on the demodulated bit sequence based on the parity check matrix and the Z,

wherein the demodulated bit sequence includes a part of an encoded code block associated with a bit position,

wherein a part of the code block is not included in the demodulated bit sequence, and

wherein the bit position is associated with the RV index and a multiple of the Z.

7. The method of claim 6 ,

wherein a length of the part of the code block is 2×Z.

8. The method of claim 6 ,

wherein the part of the code block is not received for an initial transmission and any re-transmission.

9. The method of claim 6 ,

wherein the demodulated bit sequence includes the part of the encoded code block reordered from the bit position.

10. The method of claim 6 , wherein the demodulated bit sequence includes cyclic redundancy check (CRC) bits.

11. A transmitter in a communication system, the transmitter comprising:

a transceiver; and

a controller coupled with the transceiver and configured to:

identify input bits to be transmitted,

identify a code block based on the input bits,

identify Z, a size of an identity matrix or a cyclically shifted matrix of the identity matrix,

identify a parity check matrix for a low density parity check (LDPC) encoding based on the Z,

encode the code block by the LDPC encoding based on the parity-check matrix and the Z,

identify a redundancy version (RV) index,

generate a bit sequence by a rate matching on the encoded code block based on a bit position,

modulate the bit sequence, and

transmit, via the transceiver, the modulated bit sequence,

wherein a part of the code block is not included in the encoded code block, and

the bit position is determined based on the RV index and a multiple of the Z.

12. The transmitter of claim 11 ,

wherein a length of the part of the code block is 2×Z.

13. The transmitter of claim 11 ,

wherein the part of the code block is not transmitted for an initial transmission and any re-transmission.

14. The transmitter of claim 11 ,

wherein the rate matching comprises reordering the encoded code block from the bit position.

15. The transmitter of claim 11 , wherein the encoded code block includes cyclic redundancy check (CRC) bits.

16. A receiver in a communication system, the receiver comprising:

a transceiver; and

a controller coupled with the transceiver and configured to:

receive, via the transceiver, a signal,

demodulate the received signal to identify a demodulated bit sequence,

identify Z, a size of an identity matrix or a cyclically shifted matrix of the identity matrix,

identify a parity check matrix for a low density parity check (LDPC) decoding based on the Z,

identify a redundancy version (RV) index, and

identify a code block by the LDPC decoding on the demodulated bit sequence based on the parity check matrix and the Z,

wherein the demodulated bit sequence includes a part of an encoded code block associated with a bit position,

wherein a part of the code block is not included in the demodulated bit sequence, and

wherein the bit position is associated with the RV index and a multiple of the Z.

17. The receiver of claim 16 ,

wherein a length of the part of the code block is 2×Z.

18. The receiver of claim 16 ,

wherein the part of the code block is not received for an initial transmission and any re-transmission.

19. The receiver of claim 16 ,

wherein the demodulated bit sequence includes the part of the encoded code block reordered from the bit position.

20. The receiver of claim 16 , wherein the demodulated bit sequence includes cyclic redundancy check (CRC) bits.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 24, 2021
From: JEONG, HONGSIL; KIM, KYUNGJOONG; MYUNG, SEHO
To: SAMSUNG ELECTRONICS CO., LTD
Reel/Frame 056334/0448 →
Priority Claims (5)
KR 10-2017-0036021 · Mar 22, 2017 · national
KR 10-2017-0053899 · Apr 26, 2017 · national
KR 10-2017-0101937 · Aug 10, 2017 · national
KR 10-2017-0116133 · Sep 11, 2017 · national
KR 10-2017-0128254 · Sep 29, 2017 · national
Continuity (3)
Continuation 16752134 · Jan 24, 2020
Continuation 15933220 · Mar 22, 2018
Related Publication 20210288751A1 · Sep 16, 2021
Cited By (1)
US 12,401,464