IP Library › Granted Patent US 11,677,648
Granted Patent B2
US 11,677,648 · App. 17/182,914 · Granted Jun 13, 2023

Device and method for checking frames from a communication bus

Inventor: Fred Rennig (Nandlstadt, DE)
Assignee: STMicroelectronics Application GMBH
H04L43/08H04L12/40H04L2012/40215
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Quick Facts
Patent No.
US 11,677,648
App. No.
17/182,914
Granted
Jun 13, 2023
Kind
B2
Abstract

In accordance with an embodiment, a method includes determining whether a frame received from a communication bus is encoded according to a particular communication protocol and is addressed to a particular electronic device; increasing a frame count value when the frame is encoded according to the particular communication protocol and is addressed to the particular electronic device based on the determination, wherein increasing the frame count value comprises increasing a count of a modular arithmetic counter circuit having a first bit depth, and the frame count value is constrained to a modulus value of the modular arithmetic counter circuit; setting a frame count status bit based on comparing the frame count value to threshold values, and transmitting a frame comprising the frame counter status bit over the communication bus, and resetting the frame count value at an end of a monitoring time interval.

Claims (57)

1. An electronic device configured to be coupled to a communication bus to receive therefrom digital signals arranged in frames comprising frames encoded according to a particular communication protocol, the electronic device comprising:

a check circuit sensitive to the digital signals arranged in frames, the check circuit configured to determine whether a received frame is encoded according to the communication protocol and is addressed to the electronic device;

a frame counter circuit coupled to the check circuit and configured to produce a frame count value that is a function of a number of frames received during a monitoring time interval, and to increase the frame count value as a result of a positive outcome of the determination by the check circuit, wherein the frame counter circuit comprises a modular arithmetic counter circuit having a certain bit depth, and wherein the frame count value is constrained to a modulus value of the modular arithmetic counter circuit;

a comparator circuit configured to, during the monitoring time interval:

compare the frame count value to a first frame count threshold value and, as a result of the frame count value being equal to the first frame count threshold value, set a frame counter status bit to a first value indicative of a first operating status of the electronic device, and

compare the frame count value to a second frame count threshold value different from the first frame count threshold value and, as a result of the frame count value being equal to the second frame count threshold value, set the frame counter status bit to a second value indicative of a second operating status of the electronic device, wherein the frame counter status bit is set to either the first value based on comparing the frame count value to the first frame count threshold or to the second value based on comparing the frame count value to the second frame count threshold; and

a controller circuit configured to transmit over the communication bus a frame comprising the frame counter status bit at an end of the monitoring time interval, and to reset the frame count value at the end of the monitoring time interval.

2. The electronic device of claim 1 , wherein the electronic device is configured to receive a number j of frames during the monitoring time interval, and the modular arithmetic counter circuit has a non-zero bit depth equal to or lower than an integer part of log 2 (j).

3. The electronic device of claim 1 , wherein the comparator circuit has a bit depth equal to the certain bit depth of the modular arithmetic counter circuit.

4. The electronic device of claim 1 , wherein the modular arithmetic counter circuit has a non-zero bit depth less than or equal to five.

5. The electronic device of claim 1 , further comprising at least one register configured to store the first frame count threshold value and the second frame count threshold value, wherein the at least one register is accessible via the communication bus in read mode and write mode.

6. The electronic device of claim 1 , further comprising watchdog sensing circuitry configured to sense watchdog events occurring at certain time intervals and comprising a watchdog event counter circuit configured to provide a watchdog count value of sensed watchdog events, wherein the watchdog sensing circuitry is configured to produce, as a result of a watchdog event being sensed:

a transmission over the communication bus of a frame comprising the frame counter status bit,

an increase in the watchdog count value,

a comparison of the watchdog count value to a watchdog count threshold value, and

as a result of the watchdog count value being equal to the watchdog count threshold value, a reset of the frame count value and of the watchdog count value.

7. The electronic device of claim 6 , comprising at least one register configured to store the watchdog count threshold value, wherein the at least one register is accessible via the communication bus in read mode and write mode.

8. The electronic device of claim 6 , comprising an oscillator circuit configured to generate the watchdog events at regular time intervals.

9. The electronic device of claim 6 , wherein sensing watchdog events occurring at the certain time intervals comprises receiving watchdog frames via the communication bus at regular time intervals.

10. The electronic device of claim 1 , wherein the controller circuit is configured to reset the frame count value as a result of receiving a reset command frame via the communication bus.

11. The electronic device of claim 1 , wherein the controller circuit is configured to switch the electronic device to a fail-safe operating mode as a result of the frame counter status bit having the second value indicative of the second operating status of the electronic device (D) at the end of the monitoring time interval.

12. A system comprising:

the communication bus according to claim 1 ;

at least one electronic device according to claim 1 , the at least one electronic device coupled to the communication bus; and

a further electronic device coupled to the communication bus and configured to send over the communication bus frames addressed to the at least one electronic device.

13. A vehicle comprising the system according to claim 12 .

14. An integrated circuit comprising:

a receiver configured to be coupled to a communication bus, and to receive a digital signal arranged in frames encoded according to a particular communication protocol;

a check circuit coupled to the receiver, the check circuit configured to determine whether a frame received by the receiver is encoded according to the particular communication protocol and is addressed to a particular electronic device;

a frame counter circuit coupled to the check circuit, the frame counter circuit configured to increase a frame count value when the check circuit indicates the frame is encoded according to the particular communication protocol and is addressed to the particular electronic device, wherein the frame counter circuit comprises a modular arithmetic counter circuit having a first bit depth, and the frame count value is constrained to a modulus value of the modular arithmetic counter circuit;

a comparator circuit configured to, during a monitoring time interval:

compare the frame count value to a first frame count threshold value,

set a frame counter status bit to a first value indicative of a first operating status of the particular electronic device when the frame count value is equal to the first frame count threshold value,

compare the frame count value to a second frame count threshold value different from the first frame count threshold value, and

set the frame counter status bit to a second value indicative of a second operating status of the particular electronic device when the frame count value is equal to the second frame count threshold value, wherein the frame counter status bit is set to either the first value based on comparing the frame count value to the first frame count threshold or to the second value based on comparing the frame count value to the second frame count threshold; and

a controller circuit configured to transmit a frame comprising the frame counter status bit over the communication bus at an end of the monitoring time interval, and to reset the frame count value at the end of the monitoring time interval.

15. The integrated circuit of claim 14 , wherein:

the communication bus is a Controller Area Network (CAN) communication bus; and

the particular communication protocol is a CAN Flexible Data Rate (FD) communication protocol.

16. A method, comprising:

determining whether a frame received from a communication bus is encoded according to a particular communication protocol and is addressed to a particular electronic device;

increasing a frame count value when the frame is encoded according to the particular communication protocol and is addressed to the particular electronic device based on the determination, wherein increasing the frame count value comprises increasing a count of a modular arithmetic counter circuit having a first bit depth, and the frame count value is constrained to a modulus value of the modular arithmetic counter circuit;

during a monitoring time interval:

comparing the frame count value to a first frame count threshold value, setting a frame counter status bit to a first value indicative of a first operating status of the particular electronic device when the frame count value is equal to the first frame count threshold value,

comparing the frame count value to a second frame count threshold value different from the first frame count threshold value, and

setting the frame counter status bit to a second value indicative of a second operating status of the particular electronic device when the frame count value is equal to the second frame count threshold value, wherein the frame counter status bit is set to either the first value based on comparing the frame count value to the first frame count threshold or to the second value based on comparing the frame count value to the second frame count threshold; and

transmitting a frame comprising the frame counter status bit over the communication bus at an end of the monitoring time interval, and resetting the frame count value at the end of the monitoring time interval.

17. The method of claim 16 , further comprising:

monitoring watchdog events occurring at certain time intervals; and

transmitting a frame comprising the frame counter status bit upon sensing a monitored watchdog event.

18. The method of claim 17 , further comprising:

providing a count of the sensed monitored watchdog events; and

when the count of the sensed monitored watchdog events reaches a predetermined threshold,

resetting the frame count value, and

resetting the count of the sensed watchdog events.

19. The method of claim 16 , further comprising switching the particular electronic device into a fail-safe mode when the frame counter status bit has the second value indicative of the second operating status of the particular electronic device at the end of the monitoring time interval.

20. The method of claim 19 , wherein the communication bus is a control bus of a vehicle.

Assignments (2)
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNOR'S SIGNATURE PREVIOUSLY RECORDED AT REEL: 055375 FRAME: 0428. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Aug 17, 2022
From: RENNIG, FRED
To: STMICROELECTRONICS APPLICATION GMBH
Reel/Frame 061203/0754 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 23, 2021
From: RENNIG, FRED
To: STMICROELECTRONICS APPLICATION GMBH
Reel/Frame 055375/0428 →
Priority Claims (1)
IT 102020000004978 · Mar 9, 2020 · national
Continuity (1)
Related Publication 20210281497A1 · Sep 9, 2021
Cited By (1)
US 12,332,727