Method of fabricating semiconductor device having void in bit line contact plug
A semiconductor device, a method of fabricating the semiconductor device and a memory are disclosed. In the provided semiconductor device, bit line contact plugs partially reside on insulating material layers in gate trenches in active areas and thus can come into sufficient contact with the active areas. This ensures good electrical transmission between the bit line contact plugs and the active areas even when there are internal voids in the bit line contact plugs. Such bit line contact plugs allowed to contain internal voids can be fabricated in an easier and faster manner, thus allowing a significantly enhanced memory fabrication throughput.
1. A method of fabricating a semiconductor device, comprising:
providing a substrate, in which a plurality of active areas are defined;
forming at least one gate trench in the substrate so that the gate trench is located at least partially within the plurality of active areas;
sequentially filling a buried gate and an insulating material layer in the gate trench; and
forming at least one bit line contact plug on the substrate, each formed over a portion of the insulating material layer and coupled to one of the plurality of active areas, each of the at least one bit line contact plug containing a void being formed in a portion of the bit line contact plug having a maximum width.
2. The method of claim 1 , wherein forming the at least one bit line contact plug comprises:
forming a sacrificial layer on the substrate, in which at least one bit line trench extending in a first direction is formed; and
filling the at least one bit line trench with a first conductive layer, the first conductive layer configured to form the at least one bit line contact plug, the first conductive layer containing at least one internal void.
3. The method of claim 2 , wherein forming the sacrificial layer with the at least one bit line trench comprises:
successively forming a second sacrificial material layer on the substrate and a first sacrificial material layer on the second sacrificial material layer;
patterning the first sacrificial material layer so that a first trench extending in the first direction is formed in the first sacrificial material layer; and
etching the second sacrificial material layer through the first trench in the first sacrificial material layer so that a second trench is formed in the second sacrificial material layer, wherein the second trench comprises side faces that are bulged outwardly beyond respective side faces of the first trench so that a maximum opening size of the second trench is greater than a maximum opening size of the first trench.
4. The method of claim 3 , wherein the bulged side faces of the second trench are arcuate.
5. The method of claim 3 , wherein forming the first conductive layer comprises:
filling both the first and second trenches by depositing a first conductive material on the substrate in such a manner that the void is formed in the first conductive material deposited within the second trench.
6. The method of claim 2 , wherein the bit line trench extends from a top above an upper surface of the insulating material layer to a bottom located at a predetermined depth in the insulating material layer, the bottom of the bit line contact plug located above an upper surface of the buried gate.
7. The method of claim 6 , wherein a lower portion of the bit line trench below the upper surface of the insulating material layer has a trapezoidal cross-section with a bottom base longer than a top base.
8. The method of claim 2 , further comprising, subsequent to the formation of the at least one bit line contact plug:
forming a second conductive layer on the at least one bit line contact plug, the second conductive layer having a maximum width smaller than a maximum width of the first conductive layer.
9. The method of claim 8 , wherein forming the second conductive layer comprises:
depositing a second conductive material layer on the substrate, the second conductive material layer covering the at least one bit line contact plug; and
patterning the second conductive material layer to form the second conductive layer, the second conductive layer extending over the first conductive layer in the first direction.
10. A method of fabricating a semiconductor device, comprising:
providing a substrate, in which a plurality of active areas are defined;
forming at least one gate trench in the substrate so that the gate trench is located at least partially within the plurality of active areas;
sequentially filling a buried gate and an insulating material layer in the gate trench; and
forming at least one bit line contact plug on the substrate, each formed over a portion of the insulating material layer and coupled to one of the plurality of active areas, each of the at least one bit line contact plug containing a void, wherein forming the at least one bit line contact plug comprises:
forming a sacrificial layer on the substrate, in which at least one bit line trench extending in a first direction is formed; and
filling the at least one bit line trench with a first conductive layer, the first conductive layer configured to form the at least one bit line contact plug, the first conductive layer containing at least one internal void, wherein forming the sacrificial layer with the at least one bit line trench comprises:
successively forming a second sacrificial material layer on the substrate and a first sacrificial material layer on the second sacrificial material layer;
patterning the first sacrificial material layer so that a first trench extending in the first direction is formed in the first sacrificial material layer; and
etching the second sacrificial material layer through the first trench in the first sacrificial material layer so that a second trench is formed in the second sacrificial material layer, wherein the second trench comprises side faces that are bulged outwardly beyond respective side faces of the first trench so that a maximum opening size of the second trench is greater than a maximum opening size of the first trench.
11. The method of claim 10 , wherein the bulged side faces of the second trench are arcuate.
12. The method of claim 10 , wherein forming the first conductive layer comprises:
filling both the first and second trenches by depositing a first conductive material on the substrate in such a manner that the void is formed in the first conductive material deposited within the second trench.
13. The method of claim 10 , wherein the bit line trench extends from a top above an upper surface of the insulating material layer to a bottom located at a predetermined depth in the insulating material layer, the bottom of the bit line contact plug located above an upper surface of the buried gate.
14. The method of claim 10 , wherein a lower portion of the bit line trench below the upper surface of the insulating material layer has a trapezoidal cross-section with a bottom base longer than a top base.
15. The method of claim 10 , further comprising, subsequent to the formation of the at least one bit line contact plug:
forming a second conductive layer on the at least one bit line contact plug, the second conductive layer having a maximum width smaller than a maximum width of the first conductive layer.
16. The method of claim 15 , wherein forming the second conductive layer comprises:
depositing a second conductive material layer on the substrate, the second conductive material layer covering the at least one bit line contact plug; and
patterning the second conductive material layer to form the second conductive layer, the second conductive layer extending over the first conductive layer in the first direction.