Embedded memory using SOI structures and methods

1. An integrated circuit (IC) comprising:

a semiconductor-on-insulator (SOI) substrate comprising a handle substrate, an insulator layer over the handle substrate, and a semiconductor device layer over the insulator layer;

a logic device comprising a logic gate arranged over the semiconductor device layer; and

a memory cell comprising a control gate and a select gate laterally adjacent to one another and arranged over the semiconductor device layer, wherein a charge-trapping layer underlies the control gate, the memory cell further comprising a doped region arranged in the handle substrate and an epitaxial semiconductor region extending from near an upper surface of the semiconductor device layer to an upper surface of the doped region.

2. The IC according to claim 1 , wherein the SOI substrate is a fully depleted SOI (FDSOI) substrate.

3. The IC according to claim 1 , wherein the semiconductor device layer is a monocrystalline silicon layer having a thickness ranging from 5 nm to 40 nm, and the insulator layer is a silicon dioxide or sapphire layer having a thickness ranging from 10 nm to 60 nm.

4. The IC according to claim 1 , wherein the semiconductor device layer has a thickness such that during operation of the memory cell or the logic device, a depletion region in a channel region of the memory cell or the logic device extends fully across the thickness of the semiconductor device layer.

5. The IC according to claim 1 , further comprising:

an individual source/drain region disposed to a first side of the control gate;

an intermediate source/drain region arranged laterally between a second side of the control gate and a first side of the select gate, the second side of the control gate being opposite the first side of the select gate.

6. The IC according to claim 5 , wherein the doped region is a common source/drain region arranged on to a second side of the select gate opposite the first side, wherein the common source/drain region has a lowermost portion that extends into the handle substrate.

7. The IC according to claim 6 , wherein the control gate extends in a first direction and the common source/drain region extends continuously between multiple memory cells in a second direction perpendicular to the first direction, and the common source/drain region is coupled to respective source/drain regions of the multiple memory cells.

8. The IC according to claim 5 , wherein the individual source/drain region and the intermediate source/drain region have lower portions in direct contact with an upper surface of the insulator layer of the SOI substrate.

9. The IC according to claim 8 , further comprising:

an isolation region arranged in the semiconductor device layer between the memory cell and the logic device, the isolation region extending from an upper surface of the semiconductor device layer and contacting the upper surface of the insulator layer.

10. The IC of claim 1 , wherein the doped region has an outer edge arranged directly under the select gate.

11. The IC of claim 1 , wherein the doped region has a first width as measured in a first direction parallel to an upper surface of the handle substrate, and wherein the epitaxial semiconductor region has a second width as measured in the first direction, the second width being less than the first width.

12. An integrated circuit (IC) including a memory device, comprising:

a semiconductor-on-insulator (SOI) substrate comprising a handle substrate, an insulator layer over the handle substrate, and a semiconductor device layer over the insulator layer;

first and second individual source/drain regions arranged in the semiconductor device layer and spaced apart from one another in a first direction;

first and second intermediate source/drain regions arranged in the semiconductor device layer and arranged between the first and second individual source/drain regions, the first individual source/drain region being spaced apart from the first intermediate source/drain region by a first control channel region, and the second individual source/drain region being spaced apart from the second intermediate source/drain region by a second control channel region;

a common source/drain region arranged in the semiconductor device layer and arranged between the first and second intermediate source/drain regions, the first intermediate source/drain region being spaced apart from the common source/drain region by a first select channel region, and the second intermediate source/drain region being spaced apart from the common source/drain region by a second select channel region;

first and second control gates arranged over the first and second control channel regions, respectively;

first and second select gates arranged over the first and second select channel regions, respectively, the first and second select gates extending continuously in a second direction perpendicular to the first direction to extend over multiple columns of memory cells for the memory device; and

wherein the common source/drain region extends continuously in the second direction to be coupled to respective source/drain regions of the multiple columns of memory cells for the memory device;

wherein the common source/drain region includes a doped region arranged in the handle substrate and an epitaxial semiconductor region extending from near an upper surface of the semiconductor device layer to an upper surface of the doped region.

13. The IC of claim 12 , wherein the common source/drain region has outermost edges that are arranged directly under the first and second select gates.

14. The IC of claim 12 , wherein the doped region has a first width as measured in the first direction between nearest edges of the first and second select gates, and wherein the epitaxial semiconductor region has a second width as measured in the first direction, the second width being less than the first width.

15. An integrated circuit (IC) including a memory device comprising:

a semiconductor-on-insulator (SOI) substrate comprising a handle substrate, an insulator layer over the handle substrate, and a semiconductor device layer over the insulator layer;

a memory cell comprising a control gate and a select gate laterally adjacent to one another and arranged over the semiconductor device layer, wherein a charge-trapping layer underlies the control gate; and

a common source/drain region arranged in the SOI substrate to a side of the select gate, the common source/drain region having an upper surface that corresponds to an upper surface of the semiconductor device layer and that is below a lower surface of the control gate, and having a lowermost surface below an upper surface of the handle substrate;

wherein the common source/drain region includes a doped region arranged in the handle substrate and an epitaxial semiconductor region extending from near an upper surface of the semiconductor device layer to an upper surface of the doped region.

16. The IC of claim 15 , wherein the common source/drain region extends in a continuous path between multiple common source/drain regions of multiple respective columns of the memory device.

17. The IC of claim 15 , wherein the common source/drain region has an outer edge arranged directly under the select gate.

18. The IC of claim 15 , further comprising:

a logic device comprising a logic gate arranged over the semiconductor device layer;

wherein the logic gate is spaced apart from a logic channel region within the semiconductor device layer by a high κ dielectric layer.

19. The IC according to claim 15 , further comprising:

an intermediate source/drain region disposed in the semiconductor device layer between the select gate and the control gate; and

an individual source/drain region disposed in the semiconductor device layer to a side of the control gate opposite the intermediate source/drain region.

20. The IC according to claim 19 , further comprising:

bias circuitry configured to carry out a program-inhibit operation by biasing the common source/drain region to approximately −3.5 volts, while the individual source/drain region is biased to less than +1.1 volts, while the select gate is biased to approximately −3.5 volts, and while the control gate is biased to approximately +4 volts.