Unmap data pattern for coarse mapping memory sub-system
Devices, methods, and media are described for unmap support in coarse mapped storage. In one embodiment a controller of a memory sub-system manages a set of metadata for super management units (SMU) of the memory sub-system, wherein each SMU of the memory sub-system comprises a plurality of data management units (MU), and wherein each MU comprises a plurality of addressable memory elements as part of a coarse memory storage of the memory sub-system. The controller processes a trim command for a first SMU of the plurality of SMUs, and adjusts a trim bit associated with metadata for the first SMU. This trim bit can then be used to manage read and write operations as the trimmed unit waits to be written with an unmap data pattern. Similarly, a trim bit in MU metadata can be used manage related operations to prevent memory access errors.
1. A memory controller configured to perform operations comprising:
receiving a data access command comprising an address; and
in response to the receiving of the data access command and based on a value of an unmap bit that corresponds to a portion of memory identified by the address:
writing an unmap data pattern to the identified portion of memory;
modifying the value of the unmap bit; and
processing the data access command.
2. The memory controller of claim 1 , wherein:
the receiving of the data access command comprises receiving a read command via a bus; and
the processing of the data access command comprises:
reading data from the identified portion of memory; and
providing the data via the bus.
3. The memory controller of claim 2 , wherein the operations further comprise:
after the reading of the data from the identified portion of memory, based on the writing of the unmap data pattern to the identified portion of memory, determining a cyclic redundancy check (CRC) value of the identified portion of memory; and
storing the CRC value.
4. The memory controller of claim 2 , wherein the operations further comprise:
after the reading of the data from the identified portion of memory, accessing a stored cyclic redundancy check (CRC) value of the identified portion of memory;
determining, based on the read data, a CRC value of the identified portion of memory; and
comparing the accessed CRC value with the determined CRC value to detect memory corruption.
5. The memory controller of claim 2 , wherein the operations further comprise:
receiving a second data access command comprising a second address;
in response to the receiving of the second data access command and based on a second value of a second unmap bit that corresponds to a second portion of memory identified by the second address:
bypassing a CRC check of the second portion of memory; and
processing the second data access command.
6. The memory controller of claim 1 , wherein the operations further comprise:
prior to the receiving of the data access command, receiving an unmap data command; and
based on the unmap data command, setting the value of the unmap bit that corresponds to the identified portion of memory.
7. The memory controller of claim 1 , wherein:
the receiving of the data access command comprises receiving a write command via a bus; and
the processing of the data access command comprises:
writing data to the identified portion of memory; and
providing an acknowledgement via the bus.
8. The memory controller of claim 1 , wherein the operations are performed by a processor of the memory controller, configured by instructions stored in firmware.
9. A memory system coupled to a host system, the memory system configured to:
receive an unmap data command from the host system;
based on the unmap data command, setting a value of an unmap bit that corresponds to a portion of memory; and
in response to receiving a data access command from the host system and based on the value of the unmap bit:
writing an unmap data pattern to the portion of memory;
modifying the value of the unmap bit; and
processing the data access command.
10. The memory system of claim 9 , wherein:
the receiving of the data access command comprises receiving a read command via a bus; and
the processing of the data access command comprises:
reading data from the portion of memory; and
providing the data to the host system via the bus.
11. The memory system of claim 10 , wherein the memory system is further configured to:
after the reading of the data from the portion of memory, based on the writing of the unmap data pattern to the portion of memory, determining a cyclic redundancy check (CRC) value of the portion of memory; and
storing the CRC value.
12. The memory system of claim 10 , wherein the memory system is further configured to:
after the reading of the data from the portion of memory, accessing a stored cyclic redundancy check (CRC) value of the portion of memory;
determining, based on the read data, a CRC value of the portion of memory; and
comparing the accessed CRC value with the determined CRC value to detect memory corruption.
13. The memory system of claim 10 , wherein the memory system is further configured to:
receiving, from the host system, a second data access command comprising a second address;
in response to the receiving of the second data access command and based on a second value of a second unmap bit that corresponds to a second portion of memory identified by the second address:
bypassing a CRC check of the second portion of memory; and
processing the second data access command.
14. The memory system of claim 9 , wherein:
the receiving of the data access command comprises receiving a write command via a bus; and
the processing of the data access command comprises:
writing data to the portion of memory; and
providing an acknowledgement to the host system via the bus.
15. A storage device comprising:
a memory component; and
a processing device operatively coupled with the memory component and configured to perform operations comprising:
receiving a data access command comprising an address; and
in response to the receiving of the data access command and based on a value of an unmap bit that corresponds to a portion of memory identified by the address:
writing an unmap data pattern to the identified portion of memory;
modifying the value of the unmap bit; and
processing the data access command.
16. The storage device of claim 15 , wherein:
the receiving of the data access command comprises receiving a read command via a bus; and
the processing of the data access command comprises:
reading data from the identified portion of memory; and
providing the data via the bus.
17. The storage device of claim 16 , wherein the operations further comprise:
after the reading of the data from the identified portion of memory, based on the writing of the unmap data pattern to the identified portion of memory, determining a cyclic redundancy check (CRC) value of the identified portion of memory; and
storing the CRC value.
18. The storage device of claim 16 , wherein the operations further comprise:
after the reading of the data from the identified portion of memory, accessing a stored cyclic redundancy check (CRC) value of the identified portion of memory;
determining, based on the read data, a CRC value of the identified portion of memory; and
comparing the accessed CRC value with the determined CRC value to detect memory corruption.
19. The storage device of claim 16 , wherein the operations further comprise:
receiving a second data access command comprising a second address;
in response to the receiving of the second data access command and based on a second value of a second unmap bit that corresponds to a second portion of memory identified by the second address:
bypassing a CRC check of the second portion of memory; and
processing the second data access command.
20. The storage device of claim 15 , wherein the operations further comprise:
prior to the receiving of the data access command, receiving an unmap data command; and
based on the unmap data command, setting the value of the unmap bit that corresponds to the identified portion of memory.