IP Library Granted Patent US 11,681,565
Granted Patent B2
US 11,681,565 · App. 16/131,008 · Granted Jun 20, 2023

Technologies for hierarchical clustering of hardware resources in network function virtualization deployments

Inventors: Andrey Chilikin (Limerick, IE); Sugesh Chandran (Mallow, IE)
Assignee: Intel Corporation
G06F9/5077G06F9/45558G06F2009/45595
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Quick Facts
Patent No.
US 11,681,565
App. No.
16/131,008
Filed
Sep 13, 2018
Granted
Jun 20, 2023
Kind
B2
Art Unit
2444
USPC
709/226
Abstract

Technologies for the hierarchical clustering of hardware resources in network function virtualization (NFV) deployments include a compute node that is configured to create a network function profile that includes a plurality of network functions to be deployed on the compute node. Additionally, the compute node is configured to translate the network function profile usable to identify which of the plurality of network functions are to be managed by each of the plurality of interconnected hardware resources into a hardware profile for each of a plurality of interconnected hardware resources. The compute node is further configured to deploy each of the plurality of network functions to one or more of the plurality of interconnected hardware resources based on the hardware profile. Other embodiments are described herein.

Claims (25)

1. A compute node for hierarchical clustering of hardware resources in network function virtualization (NFV) deployments, the compute node comprising:

circuitry to automatically and without user intervention:

create a network function profile that includes a plurality of network functions to be deployed on the compute node;

store the network function profile;

translate the network function profile into a plurality of accelerator profiles, each of the plurality of accelerator profiles corresponding to a respective one of a plurality of hardware accelerators included in a plurality of interconnected hardware resources that reside on the compute node, wherein the plurality of accelerator profiles are usable to identify which of the plurality of network functions are to be supported by respective one or more hardware accelerators from among the plurality of hardware accelerators;

store the plurality of accelerator profile; and

cause the plurality of network functions to be deployed to the plurality of hardware accelerators based on the stored accelerator profiles.

2. The compute node of claim 1 , wherein the plurality of interconnected hardware resources further includes at least one general purpose processor of the compute node.

3. The compute node of claim 1 , wherein the plurality of interconnected hardware resources further includes a plurality of network interface controllers communicatively coupled to a switch.

4. The compute node of claim 1 , wherein the stored network function profile includes a percentage of total network traffic to be processed for each of the plurality of network functions.

5. The compute node of claim 1 , wherein the stored network function profile includes a number of required sockets of the compute node on which each network function is to be deployed.

6. The compute node of claim 1 , wherein the stored network function profile includes a priority level for each of the plurality of network functions.

7. The compute node of claim 1 , wherein the stored network function profile comprises a hierarchical tree of the plurality of network functions based on a corresponding priority level of each of the plurality of network functions.

8. One or more non-transitory machine-readable storage media comprising a plurality of instructions stored thereon that, in response to being executed, cause a compute node to:

create, automatically and without user intervention, a network function profile that includes a plurality of network functions to be deployed on the compute node;

store the network function profile;

translate the network function profile into a plurality of accelerator profiles, each of the plurality of accelerator profiles corresponding to a respective one of a plurality of hardware accelerators included in a plurality of interconnected hardware resources that reside on the compute node, wherein the plurality of accelerator profiles are usable to identify which of the plurality of network functions are to be supported by respective one or more hardware accelerators from among the plurality of hardware accelerators;

store the plurality of accelerator profiles; and

cause the plurality of network functions to be deployed to the plurality of hardware accelerators based on the stored accelerator profiles.

9. The one or more non-transitory machine-readable storage media of claim 8 , wherein the plurality of interconnected hardware resources further includes at least one general purpose processor of the compute node.

10. The one or more non-transitory machine-readable storage media of claim 8 , wherein the plurality of interconnected hardware resources further includes a plurality of network interface controllers communicatively coupled to a switch.

11. The one or more non-transitory machine-readable storage media of claim 8 , wherein the stored network function profile includes a percentage of total network traffic to be processed for each of the plurality of network functions.

12. The one or more non-transitory machine-readable storage media of claim 8 , wherein the stored network function profile includes a number of required sockets of the compute node on which each network function is to be deployed.

13. The one or more non-transitory machine-readable storage media of claim 8 , wherein the stored network function profile includes a priority level for each of the plurality of network functions.

14. The one or more non-transitory machine-readable storage media of claim 8 , wherein the stored network function profile comprises a hierarchical tree of the plurality of network functions based on a corresponding priority level of each of the plurality of network functions.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 18, 2018
From: CHILIKIN, ANDREY; CHANDRAN, SUGESH
To: INTEL CORPORATION
Reel/Frame 046894/0686 →
Continuity (1)
Related Publication 20190042326A1 · Feb 7, 2019