Sub-FPGA level compilation platform with adjustable dynamic region for emulation/prototyping designs

1. A method of FPGA compilation for a multiple level FPGA, comprising:

partitioning an FPGA netlist into a first set of sub-FPGA netlists, such that each sub-FPGA netlist in the set fits within an upper level dynamic sub-FPGA region of a plurality of upper level dynamic sub-FPGA regions;

for each sub-FPGA netlist in the set:

further partitioning the sub-FPGA netlist into sub-sub-FPGA netlists;

determining if a number of interconnects between the sub-sub-FPGA netlists is below a pre-defined capacity;

adopting the further partitioning if an interconnects capacity is met, and assigning the sub-sub netlists to a lower level dynamic sub-FPGA region; and

rejecting the further partitioning if the interconnect capacity is exceeded, and assigning the sub-FPGA netlist to the upper level dynamic sub-FPGA region;

obtaining a final partitioning comprising upper level sub-FPGA netlists and lower level sub-FPGA netlists;

using at least one of the upper level sub-FPGA netlists or the lower level sub-FPGA netlists to obtain a corresponding set of sub-FPGA bitstreams; and

loading the set of sub-FPGA bitstreams into the FPGA.

2. The method of claim 1 , wherein the upper level dynamic sub-FPGA regions are SLR based.

3. The method of claim 1 , wherein the lower level dynamic sub-FPGA regions are nested within the upper level dynamic sub-FPGA regions, and wherein there are two or more lower level dynamic sub-FPGA regions provided in each upper level dynamic sub-FPGA region.

4. The method of claim 1 , further comprising at least one of:

performing global routing based on the final partitioning; and

performing global routing based on the final partitioning and implementing interconnects based upon the final partitioning in the plurality of upper level dynamic sub-FPGA regions.