IP Library Granted Patent US 11,681,939
Granted Patent B2
US 11,681,939 · App. 16/986,553 · Granted Jun 20, 2023

Quantum data loader

Inventor: Iordanis Kerenidis (Paris, FR)
Assignee: QC Ware Corp.
G06N10/00G06F17/16G06N10/20
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Quick Facts
Patent No.
US 11,681,939
App. No.
16/986,553
Granted
Jun 20, 2023
Kind
B2
Abstract

This disclosure relates generally to the field of quantum algorithms and quantum data loading, and more particularly to constructing quantum circuits for loading classical data into quantum states which reduces the computational resources of the circuit, e.g., number of qubits, depth of quantum circuit, and type of gates in the circuit.

Claims (144)

1. A quantum circuit for use in encoding an n-dimensional vector representing classical data into a quantum state, the quantum circuit comprising:

n qubits;

a first layer comprising an X gate applied to one of the n qubits; and

a plurality of subsequent layers that applies BS gates to the n qubits according to a binary tree pattern, wherein each BS gate is a single parametrized 2-qubit gate and a number of subsequent layers is not more than ceiling(log 2 (n)).

2. The quantum circuit of claim 1 , wherein n is a power of 2.

3. The quantum circuit of claim 1 , wherein a root node of the binary tree pattern is the qubit that the X gate is applied to.

4. The quantum circuit of claim 1 , wherein a total number of qubits in the quantum circuit is not greater than n.

5. The quantum circuit of claim 1 , wherein a total number of BS gates in the quantum circuit is not greater than n- 1 .

6. The quantum circuit of claim 1 , wherein the number of the plurality of subsequent layers is a logarithmic number of n.

7. The quantum circuit of claim 1 , wherein each BS gate has a form: BS(θ j )=[[1, 0, 0, 0], [0, cos(θ j ), sin(θ j ), 0], [0, −sin(θ j ), cos(θ j ), 0], [0, 0, 0, 11 where θ t is an angle and j is an integer indicating a location of the BS gate in the binary tree pattern.

8. The quantum circuit of claim 7 , wherein n is a power of 2, the n-dimensional vector has the form (x 1 , x 2 , . . . , x n ), and for j from 1 to n/2−1

θ

j

=

arc

cos

(

r

2

j

r

j

)

and

θ

n

2

+

j

-

1

=

arc

cos

(

x

2

j

-

1

r

n

2

+

j

-

1

)

,

 if x 2j is positive and

θ

n

2

+

j

-

1

=

2

π

-

arc

cos

(

x

2

j

-

1

r

n

2

+

j

-

1

)

,

if x 2j is negative with a definition of the parameter r that is for j from 1 to n/2−1

r

j

=

r

2

j

+

1

2

+

r

2

j

2

and

r

n

2

+

j

-

1

=

x

2

j

2

+

x

2

j

-

1

2

.

9. The quantum circuit of claim 1 , wherein the n qubits are superconducting qubits.

10. The quantum circuit of claim 1 , wherein the BS gates are implemented as reconfigurable beam splitters.

11. A method for executing a quantum circuit, the quantum circuit for use in encoding an n-dimensional vector representing classical data into a quantum state, the method comprising:

executing a first layer of the quantum circuit comprising an X gate applied to one of n qubits; and

executing a plurality of subsequent layers of the quantum circuit that applies BS gates to the n qubits according to a binary tree pattern, wherein each BS gate is a single parametrized 2-qubit gate and a number of subsequent layers is not more than ceiling(log 2 (n)).

12. The method of claim 11 , wherein n is a power of 2.

13. The method of claim 11 , wherein a root node of the binary tree pattern is the qubit that the X gate is applied to.

14. The method of claim 11 , wherein a total number of qubits in the quantum circuit is not greater than n.

15. The method of claim 11 , wherein a total number of BS gates in the quantum circuit is not greater than n- 1 .

16. A non-transitory computer-readable storage medium comprising stored instructions for executing a quantum circuit, the quantum circuit for use in encoding an n-dimensional vector representing classical data into a quantum state, the stored instructions, when executed by a computing system, cause the computing system to perform operations comprising:

executing a first layer of the quantum circuit comprising an X gate applied to one of n qubits; and

executing a plurality of subsequent layers of the quantum circuit that applies BS gates to the n qubits according to a binary tree pattern, wherein each BS gate is a single parametrized 2-qubit gate and a number of subsequent layers is not more than ceiling(log 2 (n)).

17. The non-transitory computer-readable storage medium of claim 16 , wherein n is a power of 2.

18. The non-transitory computer-readable storage medium of claim 16 , wherein a root node of the binary tree pattern is the qubit that the X gate is applied to.

19. The non-transitory computer-readable storage medium of claim 16 , wherein a total number of qubits in the quantum circuit is not greater than n.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 14, 2020
From: KERENIDIS, IORDANIS
To: QC WARE CORP.
Reel/Frame 053502/0616 →
Continuity (2)
Provisional Application 63007325 · Apr 8, 2020
Related Publication 20210319350A1 · Oct 14, 2021
Cited By (1)
US 12,585,841