Memory cell including cell transistor including control gate and charge accumulation layer
View Patent ↗A semiconductor device with large memory capacity is provided. A semiconductor device includes first to fourth insulators, a first conductor, a second conductor, and a first semiconductor, and the first semiconductor includes a first surface and a second surface. A first side surface of the first conductor is included on the first surface of the first semiconductor, and a first side surface of the first insulator is included on a second side surface of the first conductor. The second insulator is included in a region including a second side surface and a top surface of the first insulator, a top surface of the first conductor, and the second surface of the first semiconductor. The third insulator is included on a formation surface of the second insulator, and the fourth insulator is included on a formation surface of the third insulator. The second conductor is included in a region overlapping the second surface of the first semiconductor in a region where the fourth insulator is formed. The third insulator has a function of accumulating charge. A tunnel current is induced between the second surface of the first semiconductor and the third insulator with the second insulator therebetween by supply of a potential to the second conductor.
1. A semiconductor device comprising:
a first insulator;
a second insulator;
a third insulator;
a fourth insulator;
a first conductor;
a second conductor; and
a first semiconductor,
wherein the first semiconductor comprises a first surface and a second surface,
wherein a first side surface and a second side surface of the first insulator are positioned in a region overlapping the first surface of the first semiconductor with the first conductor therebetween,
wherein a first side surface of the first conductor is in direct contact with the first surface of the first semiconductor,
wherein the first side surface of the first insulator is in contact with a second side surface of the first conductor,
wherein the second insulator is in contact with the second side surface of the first insulator, a top surface of the first insulator, a top surface of the first conductor, and the second surface of the first semiconductor,
wherein the third insulator is positioned in a region overlapping the second surface of the first semiconductor with the second insulator therebetween,
wherein the fourth insulator is in contact with the third insulator,
wherein the second conductor is positioned in a region overlapping the second surface of the first semiconductor with the second insulator, the third insulator, and the fourth insulator therebetween,
wherein the second conductor is in contact with the fourth insulator,
wherein the third insulator is configured to accumulate charge, and
wherein a tunnel current is induced between the second surface of the first semiconductor and the third insulator with the second insulator therebetween by supply of a potential to the second conductor.
2. The semiconductor device according to claim 1 ,
wherein the third insulator is positioned also in a region overlapping the first surface of the first semiconductor.
3. The semiconductor device according to claim 1 ,
wherein a film thickness of the first semiconductor at the second surface of the first semiconductor is smaller than a film thickness of the first semiconductor at the first surface of the first semiconductor.
4. The semiconductor device according to claim 1 ,
wherein the first semiconductor comprises a metal oxide, and
wherein the second surface of the first semiconductor and a vicinity of the second surface have a higher concentration of oxygen than the first surface of the first semiconductor and a vicinity of the first surface.
5. The semiconductor device according to claim 4 ,
wherein the first surface of the first semiconductor and a vicinity of the first surface each comprise a compound constituted of an element comprised in the first conductor and an element comprised in the first semiconductor.
6. The semiconductor device according to claim 1 ,
wherein the first semiconductor comprises silicon, and
wherein, in the first surface of the first semiconductor and a vicinity of the first surface, a low-resistance region is formed of an element comprised in the first conductor and an element comprised in the first semiconductor.
7. A semiconductor wafer comprising:
a plurality of the semiconductor devices according to claim 1 ; and
a region for dicing.
8. A memory device comprising:
the semiconductor device according to claim 1 ; and
a peripheral circuit.
9. An electronic device comprising:
the memory device according to claim 8 ; and
a housing.