IP Library Granted Patent US 11,682,689
Granted Patent B2
US 11,682,689 · App. 17/128,604 · Granted Jun 20, 2023

Electronic device image sensor

Inventors: Francois Roy (Seyssins, FR); Sonarith Chhun (Pontcharra, FR)
Assignee: STMicroelectronics (Crolles 2) SAS
H01L27/14636H01L27/14632H01L27/14685H01L27/14687H01L27/1464
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 11,682,689
App. No.
17/128,604
Granted
Jun 20, 2023
Kind
B2
Abstract

An electronic device includes a substrate semiconductor wafer with semiconductor portions separated from one another by through-passages. Electronic circuits and a dielectric layer with a network of electrical connections are formed at a front face of the substrate semiconductor wafer. Electrically conductive fillings are contained within the through-passages and are connected to the network of electrical connections. Interior dielectric layers for anti-diffusion protection are provided in the through-passages between the electrically conductive fillings and the semiconductor portions. Back side dielectric layers are joined to the interior dielectric layers.

Claims (25)

1. A method for fabrication of an electronic device, comprising:

forming primary blind grooves in a semiconductor substrate wafer, said primary blind grooves extending into the semiconductor substrate wafer from a front face of the semiconductor substrate wafer and running in a longitudinal and transverse direction and intersecting one another;

forming dielectric anti-diffusion layers against sides and bottoms of the primary blind grooves to define secondary blind grooves;

filling at least a portion of the secondary blind grooves with a temporary material;

fabricating electronic circuits at the semiconductor substrate wafer;

forming a dielectric layer which includes a network of electrical connections over the front face of the semiconductor substrate wafer;

thinning the semiconductor substrate wafer starting from a back face of the semiconductor substrate wafer until at least reaching back faces of the filling in the secondary blind grooves so as to obtain a plurality of semiconductor portions separated from one another by through-passages;

removing back parts of the dielectric anti-diffusion layers so as to obtain interior anti-diffusion layers at sides of the plurality of semiconductor portions;

replacing the filling of temporary material with an electrically conductive fill that is in electrical connection with the network of electrical connections; and

forming back dielectric anti-diffusion layers.

2. The method according to claim 1 , further comprising:

after obtaining the interior anti-diffusion layers, further thinning of the semiconductor substrate wafer; and

forming the back dielectric layers on back faces of the plurality of semiconductor portions, said back dielectric layers being attached to the interior dielectric layers.

3. The method according to claim 1 , further comprising:

replacing back parts of the electrically conductive fill within the through-passages with back anti-diffusion layers.

4. The method according to claim 1 , further comprising:

forming back cavities in the back anti-diffusion layers; and

filling the back cavities with a metal material.

5. The method according to claim 1 , wherein said electronic circuits include photodiodes.

6. The method according to claim 1 , further comprising providing a polysilicon portion to make the electrical connection between the electrically conductive fill and the network of electrical connections.

7. The method according to claim 1 , wherein said electrically conductive fill includes a metal portion.

8. The method according to claim 1 , wherein filling at least said portion of the secondary blind grooves with the temporary material comprises filling a lower portion of the secondary blind grooves with the temporary material, and further comprising filling an upper portion of the secondary blind grooves with a conductive material.

9. The method according to claim 8 , wherein said conductive material filling the upper portion of the secondary blind grooves is a polysilicon material.

10. The method according to claim 1 , wherein thinning the semiconductor substrate wafer comprises thinning the semiconductor substrate wafer until past the back faces of the filling in the secondary blind grooves.

11. The method according to claim 10 , wherein forming back dielectric anti-diffusion layers comprises forming the back dielectric anti-diffusion layers coplanar with the back faces of the filling in the secondary blind grooves.

Priority Claims (1)
FR 1761836 · Dec 8, 2017 · national
Continuity (2)
Division 16212790 · Dec 7, 2018
Related Publication 20210111214A1 · Apr 15, 2021