IP Library › Granted Patent US 11,682,732
Granted Patent B2
US 11,682,732 · App. 17/184,708 · Granted Jun 20, 2023

Semiconductor substrate and display device

Inventors: Hirotaka Hayashi (Tokyo, JP); Masataka Ikeda (Tokyo, JP)
Assignee: Japan Display Inc.
H01L29/7869G02F1/167
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Quick Facts
Patent No.
US 11,682,732
App. No.
17/184,708
Granted
Jun 20, 2023
Kind
B2
Abstract

According to one embodiment, a semiconductor layer includes a base, a scanning line disposed over the base, a signal line disposed over the base, a transistor overlapping the scanning line and the signal line and including a first oxide semiconductor layer connected to the signal line, and second oxide semiconductor layers disposed in a same layer as the first oxide semiconductor layer. The second oxide semiconductor layers are disposed around the transistor, and the second oxide semiconductor layers are floating.

Claims (53)

1. A semiconductor substrate comprising:

a base;

a first insulating layer over the base;

a second insulating layer over the first insulating layer;

a scanning line disposed between the base and the first insulating layer;

a signal line disposed between the first insulating layer and the second insulating layer;

a transistor overlapping the scanning line and the signal line and comprising a first oxide semiconductor layer connected to the signal line; and

a plurality of second oxide semiconductor layers disposed around the transistor, wherein

an entire upper surface, which is a surface facing the second insulating layer, of each of the second oxide semiconductor layers is in contact with the second insulating layer,

an entire bottom surface, which is a surface facing the first insulating layer, of each of the second oxide semiconductor layers is in contact with the first insulating layer, and

no conductive wiring is electrically connected to the second oxide semiconductor layers.

2. The semiconductor substrate according to claim 1 , wherein

each of the second oxide semiconductor layers is not connected to the transistor.

3. The semiconductor substrate according to claim 1 , wherein the second oxide semiconductor layers overlap the scanning line.

4. The semiconductor substrate according to claim 1 , further comprising a capacitance electrode between the first insulating layer and the second insulating layer, wherein

the second oxide semiconductor layers do not overlap the capacitance electrode.

5. The semiconductor substrate according to claim 1 , wherein the second oxide semiconductor layers are arranged along the signal line.

6. The semiconductor substrate according to claim 1 , wherein

each of the second oxide semiconductor layers is formed in an island shape, and

a size of each of the second oxide semiconductor layers is smaller than a size of the first oxide semiconductor layer.

7. The semiconductor substrate according to claim 1 , wherein the second oxide semiconductor layers do not overlap either of the scanning line and the signal line.

8. A display device comprising:

a semiconductor substrate comprising

a first base,

a first insulating layer over the first base,

a second insulating layer over the first insulating layer,

a scanning line disposed between the first base and the first insulating layer,

a signal line disposed between the first insulating layer and the second insulating layer,

a transistor overlapping the scanning line and the signal line and comprising a first oxide semiconductor layer connected to the signal line,

a pixel electrode electrically connected to the transistor, and

a second oxide semiconductor layer disposed close to the transistor;

a counter-substrate comprising

a second base opposed to the pixel electrode, and

a counter-electrode located between the second base and the pixel electrode and opposed to the pixel electrode; and

a display function layer located between the pixel electrode and the counter-electrode and subjected to a voltage applied between the pixel electrode and the counter-electrode, wherein

an entire upper surface, which is a surface facing the second insulating layer, of the second oxide semiconductor layer is in contact with the second insulating layer,

an entire bottom surface, which is a surface facing the first insulating layer, of the second oxide semiconductor layer is in contact with the first insulating layer, and

no conductive wiring is electrically connected to the second oxide semiconductor layers.

9. The display device according to claim 8 , wherein

the second oxide semiconductor layer is not connected to the transistor.

10. The display device according to claim 8 , wherein the second oxide semiconductor layer overlaps the scanning line.

11. The display device according to claim 8 , wherein

the display device comprises a plurality of the second oxide semiconductor layers, and

the second oxide semiconductor layers do not overlap either of the scanning line and the signal line.

12. The display device according to claim 8 , wherein the display function layer is an electrophoretic layer.

13. The display device according to claim 8 , wherein the display function layer is a liquid crystal layer.

14. The display device according to claim 8 , further comprising a capacitance electrode between the first insulating layer and the second insulating layer, wherein

the display device comprises a plurality of the second oxide semiconductor layers, and

the second oxide semiconductor layers do not overlap the capacitance electrode.

15. The display device according to claim 14 , wherein the second oxide semiconductor layers are arranged along the signal line.

16. The display device according to claim 15 , wherein

the display device comprises a plurality of the second oxide semiconductor layers adjacent to the first oxide semiconductor layer, and

each of the second oxide semiconductor layers is formed in an island shape.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 22, 2025
From: JAPAN DISPLAY INC.
To: MAGNOLIA WHITE CORPORATION
Reel/Frame 072130/0313 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 25, 2021
From: HAYASHI, HIROTAKA; IKEDA, MASATAKA
To: JAPAN DISPLAY INC.
Reel/Frame 055405/0373 →
Priority Claims (1)
JP JP2020-033370 · Feb 28, 2020 · national
Continuity (1)
Related Publication 20210273108A1 · Sep 2, 2021