Class-D amplifier with deadtime distortion compensation
A class-D amplifier including a pulse width modulator including an input configured to receive a first signal based on an input signal, and an output configured to generate a pulse width modulated (PWM) signal; an H-bridge including an input coupled to an output of the pulse width modulator and an output coupled to a load, wherein the H-bridge is configured to generate an output signal across the load based on the PWM signal; and a deadtime compensation circuit coupled to the H-bridge, wherein the deadtime compensation circuit is configured to compensate for deadtime distortion in the output signal. The deadtime compensation circuit may be a feedback circuit between an output of the H-bridge and an input of the pulse width modulator, a pulse modification circuit at the output of the pulse width modulator, or an offset signal generating circuit providing an offset signal to the pulse width modulator.
1. An apparatus, comprising:
a pulse width modulator including an input configured to receive a first signal based on an input signal, and an output configured to generate a pulse width modulated (PWM) signal;
an H-bridge including an input coupled to the output of the pulse width modulator and an output coupled to a load, wherein the H-bridge is configured to generate an output signal across the load based on the PWM signal; and
a deadtime compensation circuit coupled to the H-bridge, wherein the deadtime compensation circuit is configured to compensate for deadtime distortion in the output signal, wherein the deadtime compensation circuit is coupled between the output of the H-bridge and the input of the pulse width modulator, and wherein the deadtime compensation circuit comprises:
a first signal subtractor including a first input coupled to the output of the H-bridge, and a second input coupled to the output of the pulse width modulator;
a low pass filter including an input coupled to an output of the first signal subtractor; and
a signal scalar including an input coupled to an output of the low pass filter and an output coupled to the input of the pulse width modulator.
2. The apparatus of claim 1 , wherein the signal scalar is configured to scale a signal at the output of the low pass filter by substantially one over a pulse width modulation gain of the pulse width modulator.
3. The apparatus of claim 2 , further comprising a second signal subtractor including a first input configured to receive a second signal based on the input signal, a second input coupled to the output of the signal scalar, and an output configured to produce the first signal.
4. The apparatus of claim 3 , further comprising a loop filter configured to generate the second signal based on a difference between the output signal and the input signal.
5. The apparatus of claim 4 , further comprising a third signal subtractor including a first input configured to receive the input signal, a second input configured to receive the output signal, and an output configured to generate a third signal based on the difference between the output signal and the input signal, wherein the loop filter is configured to generate the second signal based on the third signal.
6. The apparatus of claim 1 , further comprising an aliasing error compensation circuit including inputs coupled to the input and the output of the pulse width modulator, respectively, and an output coupled to the input of the pulse width modulator.
7. The apparatus of claim 6 , wherein the aliasing error compensation circuit is configured to generate a compensation signal based on the first signal and the PWM signal, wherein the first signal is based on the compensation signal and the input signal.
8. The apparatus of claim 6 , wherein the aliasing error compensation circuit comprises:
a first low pass filter (LPF) including an input coupled to the input of the pulse width modulator;
a second LPF including an input coupled to the output of the pulse width modulator;
a signal scalar including an input coupled to an output of the second LPF;
a second signal subtractor including inputs coupled to outputs of the first LPF and the signal scalar; and
a third signal subtractor including a first input configured to receive a second signal, a second input coupled to an output of the second signal subtractor, and an output coupled to the input of the pulse width modulator.
9. The apparatus of claim 1 , wherein the PWM signal comprises a differential PWM signal, wherein the output signal comprises a differential output signal, and wherein the deadtime compensation circuit comprises an operational amplifier including a differential input configured to receive the differential PWM and output signals, and feedback resistors and capacitors coupled in parallel between a differential output and the differential input of the operational amplifier.
10. The apparatus of claim 1 , wherein the deadtime compensation circuit comprises a pulse modification circuit including an input coupled to the output of the pulse width modulator and an output coupled to an input of an H-bridge driver, wherein the H-bridge driver includes an output coupled to the input of the H-bridge.
11. The apparatus of claim 10 , wherein the deadtime compensation circuit further comprises a current polarity sensor configured to generate a current polarity signal indicative of a direction of a load current through the load, wherein the current polarity sensor includes an output, at which the current polarity signal is generated, coupled to an input of the pulse modification circuit.
12. The apparatus of claim 11 , wherein the H-bridge comprises:
a positive-portion configured to generate the load current flowing through the load in a positive direction; and
a negative-portion configured to generate the load current flowing through the load in a negative direction.
13. The apparatus of claim 12 , wherein the PWM signal comprises first and second PWM signals, wherein the pulse modification circuit is configured to delay a first transition of a first PWM signal to generate a first modified PWM signal based on the current polarity signal indicating the load current flowing in the positive direction, wherein the H-bridge driver is configured to generate a first control signal based on the first modified PWM signal, and wherein the positive-portion of the H-bridge is configured to generate the load current based on the first control signal.
14. The apparatus of claim 13 , wherein the pulse modification circuit is configured to delay a second transition of the second PWM signal to generate a second modified PWM signal based on the current polarity signal indicating the load current flowing in the positive direction, wherein the H-bridge driver is configured to generate a second control signal based on the second modified PWM signal, and wherein the positive-portion of the H-bridge is configured to generate the load current based on the second control signal.
15. The apparatus of claim 12 , wherein the PWM signal comprises first and second PWM signals, wherein the pulse modification circuit is configured to delay a first transition of a first PWM signal to generate a first modified PWM signal based on the current polarity signal indicating the load current flowing in the negative direction, wherein the H-bridge driver is configured to generate a first control signal based on the first modified PWM signal, and wherein the negative-portion of the H-bridge is configured to generate the load current based on the first control signal.
16. The apparatus of claim 15 , wherein the pulse modification circuit is configured to delay a second transition of the second PWM signal to generate a second modified PWM signal based on the current polarity signal indicating the load current flowing in the negative direction, wherein the H-bridge driver is configured to generate a second control signal based on the second modified PWM signal, and wherein the negative-portion of the H-bridge is configured to generate the load current based on the second control signal.
17. The apparatus of claim 1 , wherein the deadtime compensation circuit comprises an offset signal generating circuit configured to generate an offset signal, wherein the offset signal generating circuit includes an output, at which the offset signal is generated, coupled to an input of the pulse width modulator.
18. The apparatus of claim 17 , wherein the pulse width modulator includes an output coupled to an input of an H-bridge driver, wherein the H-bridge driver includes an output coupled to the input of the H-bridge.
19. The apparatus of claim 18 , wherein the H-bridge comprises:
a positive-portion configured to generate a load current flowing through the load in a positive direction; and
a negative-portion configured to generate the load current flowing through the load in a negative direction.
20. The apparatus of claim 19 , wherein the offset signal generating circuit is configured to generate the offset signal to delay a transition in the PWM signal based on the load current flowing in the positive direction, wherein the H-bridge driver is configured to generate a control signal based on the PWM signal, and wherein the positive-portion of the H-bridge is configured to generate the load current based on the control signal.
21. The apparatus of claim 19 , wherein the offset signal generating circuit is configured to generate the offset signal to delay a transition in the PWM signal based on the load current flowing in the negative direction, wherein the H-bridge driver is configured to generate a control signal based on the PWM signal, and wherein the negative-portion of the H-bridge is configured to generate the load current based on the control signal.
22. A method, comprising:
generating a pulse width modulated signal based on an input signal;
generating an output signal across a load based on the pulse width modulated signal; and
modifying the output signal to compensate for deadtime distortion in the output signal, wherein modifying the output signal comprises modifying the pulse width modulated signal or modifying the generation of the pulse width modulated signal.
23. The method of claim 22 , wherein modifying the output signal comprises:
generating a first signal based on a difference between the output signal and the pulse width modulated signal;
filtering the first signal to generate a second signal;
scaling the second signal to generate a third signal; and
generating a fourth signal based on a difference between the third signal and the input signal, wherein the pulse width modulated signal is based on the fourth signal.
24. An apparatus, comprising:
means for generating a pulse width modulated signal based on an input signal;
means for generating an output signal across a load based on the pulse width modulated signal; and
means for modifying the output signal to compensate for deadtime distortion in the output signal, wherein means for modifying the output signal comprises means for modifying the pulse width modulated signal or the generation of the pulse width modulated signal.
25. The apparatus of claim 24 , wherein modifying the output signal comprises:
means for generating a first signal based on a difference between the output signal and the pulse width modulated signal;
means for filtering the first signal to generate a second signal;
means for scaling the second signal to generate a third signal; and
means for generating a fourth signal based on a difference between the third signal and the input signal, wherein the pulse width modulated signal is based on the fourth signal.
26. An apparatus, comprising:
a pulse width modulator including an input configured to receive a first signal based on an input signal, and an output configured to generate a pulse width modulated (PWM) signal;
an H-bridge including an input coupled to the output of the pulse width modulator and an output coupled to a load, wherein the H-bridge is configured to generate an output signal across the load based on the PWM signal; and
a deadtime compensation circuit coupled to the H-bridge, wherein the deadtime compensation circuit is configured to compensate for deadtime distortion in the output signal, wherein the deadtime compensation circuit comprises a pulse modification circuit including an input coupled to the output of the pulse width modulator and an output coupled to an input of an H-bridge driver, wherein the H-bridge driver includes an output coupled to the input of the H- bridge.
27. The apparatus of claim 26 , wherein the deadtime compensation circuit further comprises a current polarity sensor configured to generate a current polarity signal indicative of a direction of a load current through the load, wherein the current polarity sensor includes an output, at which the current polarity signal is generated, coupled to an input of the pulse modification circuit.