Resistive random access memory integrated with vertical transport field effect transistors
A semiconductor structure may include two vertical transport field effect transistors comprising a top source drain, a bottom source drain, and an epitaxial channel and a resistive random access memory between the two vertical transport field effect transistors, the resistive random access memory may include an oxide layer, a top electrode, and a bottom electrode, wherein the oxide layer may contact the top source drain of the two vertical field effect transistor. The top source drain may function as the bottom electrode of the resistive random access memory. The semiconductor structure may include a shallow trench isolation between the two vertical transport field effect transistors, the shallow trench isolation may be embedded in a first spacer, a doped source, and a portion of a substrate.
1. A semiconductor structure comprising:
a first vertical transistor adjacent to a second vertical transistor;
a resistive random access memory physically positioned between the first vertical transistor and the second vertical transistor.
2. The semiconductor structure of claim 1 , wherein the resistive random access memory directly contacts top source drain regions of both the first vertical transistor and the second vertical transistor.
3. The semiconductor structure of claim 1 , wherein the resistive random access memory directly contacts faceted sidewalls of top source drain regions of both the first vertical transistor and the second vertical transistor.
4. The semiconductor structure of claim 1 , wherein an oxide layer of the resistive random access memory directly contacts faceted sidewalls of top source drain regions of both the first vertical transistor and the second vertical transistor.
5. The semiconductor structure of claim 1 , wherein top source drains for each of the first vertical transistor and the second vertical transistor function as bottom electrodes of the resistive random access memory.
6. The semiconductor structure of claim 1 , wherein a first vertical sidewall of an oxide layer of the resistive random access memory is coplanar with a vertical sidewall of a channel region of the first vertical transistor.
7. The semiconductor structure of claim 6 , wherein a second vertical sidewall of the oxide layer of the resistive random access memory is coplanar with a vertical sidewall of a channel region of the second vertical transistor.
8. A semiconductor structure comprising:
a first vertical transistor adjacent to a second vertical transistor;
a resistive random access memory physically disposed between the first vertical transistor and the second vertical transistor, wherein a portion of the resistive random access memory is below uppermost surfaces of top source drain regions of the two vertical transistors.
9. The semiconductor structure of claim 8 , wherein the resistive random access memory directly contacts the top source drain regions of both the first vertical transistor and the second vertical transistor.
10. The semiconductor structure of claim 8 , wherein the resistive random access memory directly contacts faceted sidewalls of the top source drain regions of both the first vertical transistor and the second vertical transistor.
11. The semiconductor structure of claim 8 , wherein an oxide layer of the resistive random access memory directly contacts faceted sidewalls of the top source drain regions of both the first vertical transistor and the second vertical transistor.
12. The semiconductor structure of claim 8 , wherein the top source drains for each of the first vertical transistor and the second vertical transistor function as bottom electrodes of the resistive random access memory.
13. The semiconductor structure of claim 8 , wherein a first vertical sidewall of an oxide layer of the resistive random access memory is coplanar with a vertical sidewall of a channel region of the first vertical transistor.
14. The semiconductor structure of claim 13 , wherein a second vertical sidewall of the oxide layer of the resistive random access memory is coplanar with a vertical sidewall of a channel region of the second vertical transistor.
15. A semiconductor structure comprising:
two vertical transistors each comprising a top source drain, a bottom source drain, and an epitaxial channel; and
a resistive random access memory physically disposed between the two vertical transistors, the resistive random access memory comprising an oxide layer, a top electrode, and a bottom electrode, wherein the oxide layer contacts the top source drains of the two vertical field effect transistor.
16. The semiconductor structure of claim 15 , wherein the resistive random access memory directly contacts faceted sidewalls of the top source drains of the two vertical field effect transistors.
17. The semiconductor structure of claim 15 , wherein the oxide layer of the resistive random access memory directly contacts faceted sidewalls of the top source drains of the two vertical field effect transistors.
18. The semiconductor structure of claim 15 , wherein the top source drains of the two vertical field effect transistors function as bottom electrodes of the resistive random access memory.
19. The semiconductor structure of claim 15 , wherein a first vertical sidewall of the oxide layer of the resistive random access memory is coplanar with a vertical sidewall of a channel region of at least one of the two vertical field effect transistors.
20. The semiconductor structure of claim 19 , wherein a second vertical sidewall of the oxide layer of the resistive random access memory is coplanar with a vertical sidewall of a channel region of the second vertical transistor.