Memory device with a plurality of metal chalcogenide layers
A memory device including a first conductive layer; a second conductive layer; a resistance change region provided between the first conductive layer and the second conductive layer; a first region provided between the resistance change region and the first conductive layer, the first region including a first element selected from the group consisting of niobium, vanadium, tantalum, and titanium, and a second element selected from the group consisting of oxygen, sulfur, selenium, and tellurium, the first region having a first atomic ratio of the first element to the second element; and a second region provided between the first region and the resistance change region, the second region including the first element and the second element, the second region having a second atomic ratio of the first element to the second element, the second atomic ratio being smaller than the first atomic ratio.
1. A memory device comprising:
a first conductive layer;
a second conductive layer;
a resistance change region provided between the first conductive layer and the second conductive layer;
a first region provided between the resistance change region and the first conductive layer, the first region including a first element selected from the group consisting of niobium (Nb), vanadium (V), tantalum (Ta), and titanium (Ti), and a second element selected from the group consisting of oxygen (O), sulfur (S), selenium (Se), and tellurium (Te), the first region having a first atomic ratio of the first element to the second element; and
a second region provided between the first region and the resistance change region, the second region including the first element and the second element, the second region having a second atomic ratio of the first element to the second element, the second atomic ratio being smaller than the first atomic ratio.
2. The memory device according to claim 1 , further comprising a third region provided between the second region and the resistance change region, the third region including the first element and the second element, the third region having a third atomic ratio of the first element to the second element, the third atomic ratio being larger than the second atomic ratio.
3. The memory device according to claim 1 , wherein the second atomic ratio is equal to or less than 80% of the first atomic ratio.
4. The memory device according to claim 1 , further comprising a third conductive layer provided between the second region and the resistance change region.
5. The memory device according to claim 1 , wherein
the first region has a thickness equal to or less than 1 nm in a direction from the first conductive layer to the second conductive layer, and
the second region has a thickness equal to or less than 1 nm in the direction.
6. The memory device according to claim 1 , wherein the first conductive layer has an oriented structure.
7. A memory device comprising:
a first conductive layer;
a second conductive layer;
a resistance change region provided between the first conductive layer and the second conductive layer;
a first region provided between the resistance change region and the first conductive layer, the first region including a first substance selected from the group consisting of carbon, niobium sulfide, tantalum sulfide, titanium sulfide, niobium selenide, tantalum selenide, tantalum telluride, bismuth selenide, indium selenide, and gallium telluride;
a second region provided between the first region and the resistance change region, the second region including a second substance selected from the group consisting of molybdenum sulfide, tungsten sulfide, molybdenum selenide, tungsten selenide, molybdenum telluride, tungsten telluride, zirconium sulfide, zirconium selenide, hafnium sulfide, and hafnium selenide; and
a third region provided between the second region and the resistance change region, the third region including the first substance.
8. The memory device according to claim 7 , wherein
the first region has a thickness equal to or less than 1 nm in a direction from the first conductive layer to the second conductive layer, and
the second region has a thickness equal to or less than 1 nm in the direction.
9. The memory device according to claim 7 , wherein the first conductive layer has an oriented structure.
10. A memory device comprising:
a plurality of first wires;
a plurality of second wires intersecting with the first wires; and
a memory cell disposed in at least one of regions where the first wires intersect with the second wires, wherein
the memory cell includes:
a resistance change region provided between the first wire and the second wire;
a first region provided between the resistance change region and the first wire, the first region including a first element selected from the group consisting of niobium (Nb), vanadium (V), tantalum (Ta), and titanium (Ti), and a second element selected from the group consisting of oxygen (O), sulfur (S), selenium (Se), and tellurium (Te), the first region having a first atomic ratio of the first element to the second element; and
a second region provided between the first region and the resistance change region, the second region including the first element and the second element, the second region having a second atomic ratio of the first element to the second element, the second atomic ratio being smaller than the first atomic ratio.
11. The memory device according to claim 10 , wherein the memory cell includes a third region provided between the second region and the resistance change region, the third region including the first element and the second element, the third region having a third atomic ratio of the first element to the second element, the third atomic ratio being larger than the second atomic ratio.
12. The memory device according to claim 10 , wherein the second atomic ratio is equal to or less than 80% of the first atomic ratio.
13. The memory device according to claim 10 , wherein the memory cell further includes a conductive layer between the second region and the resistance change region.
14. The memory device according to claim 10 , wherein the first region has a thickness equal to or less than 1 nm in a direction from the first wire to the second wire, and
the second region has a thickness equal to or less than 1 nm in the direction.
15. A memory device comprising:
a first conductive layer;
a second conductive layer;
a resistance change region provided between the first conductive layer and the second conductive layer;
a first region provided between the resistance change region and the first conductive layer, the first region including a first substance selected from the group consisting of carbon, niobium sulfide, tantalum sulfide, titanium sulfide, niobium selenide, tantalum selenide, tantalum telluride, bismuth selenide, indium selenide, and gallium telluride;
a second region provided between the first region and the resistance change region, the second region including a second substance selected from the group consisting of molybdenum sulfide, tungsten sulfide, molybdenum selenide, tungsten selenide, molybdenum telluride, tungsten telluride, zirconium sulfide, zirconium selenide, hafnium sulfide, and hafnium selenide; and
a third conductive layer provided between the second region and the resistance change region,
wherein
the first region has a thickness equal to or less than 1 nm in a direction from the first conductive layer to the second conductive layer, and
the second region has a thickness equal to or less than 1 nm in the direction.