Capacitance detection method and circuit

1. A capacitance detection method, N first offsetting processes and M second offsetting processes constituting a detection period during detection, wherein N, M≥1, the method comprising:

performing charging, base capacitance offsetting, and charge transferring successively on a capacitor to be detected in an i-th first offsetting process of the first offsetting processes, to generate a first output voltage, wherein i≤N;

performing discharging, base capacitance offsetting, and charge transferring on the capacitor to be detected successively in a j-th second offsetting process of the second offsetting processes, to generate a second output voltage, wherein j≤M; and

determining a capacitance variation of the capacitor to be detected before and after the capacitor to be detected is affected by an external electric field based on the first output voltages corresponding to the N first offsetting processes and the second output voltages corresponding to the M second offsetting processes in the detection period,

wherein performing the base capacitance offsetting on the capacitor to be detected in the i-th first offsetting process comprises: performing a plurality of times of first offsetting operations on the capacitor to be detected until charges corresponding the base capacitance of the capacitor to be detected are offset in the i-th first offsetting process, each of the plurality of times of first offsetting operations comprising: charging an offset capacitor to a voltage of a voltage source Vcc minus a voltage source Vss; and performing charge offsetting on the capacitor to be detected through the charged offset capacitor; and

wherein performing the base capacitance offsetting on the capacitor to be detected in the j-th second offsetting process comprises: performing a plurality of times of second offsetting operations on the capacitor to be detected until the charges corresponding the base capacitance of the capacitor to be detected are offset in the j-th second offsetting process, each of the plurality of times of second offsetting operations comprising: charging an offset capacitor to a voltage of a voltage source Vss minus a voltage source Vcc; and performing charge offsetting on the capacitor to be detected through the charged offset capacitor.

2. The method according to claim 1 , further comprising: switching between the first offsetting process and the second offsetting process under the control of a first switching module.

3. The method according to claim 2 , wherein the first switching module comprises at least three first switches, wherein at least one of the first switches is provided in a driving module configured to charge the capacitor to be detected in a first offsetting stage or discharge the capacitor to be detected in a second offsetting stage, and at least two other first switches of the first switches are provided in an offsetting module configured to perform base capacitance offsetting on the capacitor to be detected.

4. The method according to claim 1 , further comprising: charging and discharging the offset capacitor by the offsetting module under the control of a third switching module, to perform base capacitance offsetting on the capacitor to be detected in the i-th first offsetting process or the j-th second offsetting process.

5. The method according to claim 4 , wherein the charging and discharging the offset capacitor under the control of a third switching module, to perform base capacitance offsetting on the capacitor to be detected in the i-th first offsetting process comprises: charging and discharging the offset capacitor under the control of the third switching module such that a voltage of the capacitor to be detected is decreased to implement base capacitance offsetting on the capacitor to be detected.

6. The method according to claim 5 , wherein the third switching module comprises at least two third switches, and the at least two third switches are provided in the offsetting module.

7. The method according to claim 4 , wherein the charging and discharging the offset capacitor by the offsetting module under the control of a third switching module, to perform base capacitance offsetting on the capacitor to be detected in the i-th first offsetting process or the j-th second offsetting process comprises: charging and discharging the offset capacitor under the control of the third switching module such that the voltage of the capacitor to be detected is increased to implement base capacitance offsetting on the capacitor to be detected.

8. The method according to claim 1 , wherein under the control of a fourth switching module, charge transferring on the capacitor to be detected is performed in the i-th first offsetting process or charge transferring on the capacitor to be detected is performed in the j-th second offsetting process.

9. The method according to claim 8 , wherein the fourth switching module comprises at least one fourth switch, and the fourth switch is configured to enable the capacitor to be detected to be in a charge transferring state in the i-th first offsetting process, or enable the capacitor to be detected to be in a charge transferring state in the j-th second offsetting process.

10. The method according to claim 1 , wherein the N first offsetting processes precede the M second offsetting processes, or the i-th first offsetting process alternates with the j-th second offsetting process.

11. The method according to claim 1 , wherein N=M, and i=j.

12. A capacitance detection circuit, comprising: a control module, a driving module, an offsetting module, a charge transfer module, and a processing module; N first offsetting processes and M second offsetting processes constituting a detection period during detection, wherein N, M≥1;

the control module is configured to control the driving module, the offsetting module, and the charge transfer module performing charging, base capacitance offsetting, and charge transferring successively on a capacitor to be detected in an i-th first offsetting process of the first offsetting processes, respectively, to generate a first output voltage, wherein i≤N;

the control module is configured to control the driving module, the offsetting module, and the charge transfer module performing discharging, base capacitance offsetting, and charge transferring on the capacitor to be detected successively in a j-th second offsetting process of the second offsetting processes, respectively, to generate a second output voltage, wherein j≤M; and

the processing module is configured to determine a capacitance variation of the capacitor to be detected before and after the capacitor to be detected is affected by an external electric field based on the first output voltages corresponding to the N first offsetting processes and the second output voltages corresponding to the M second offsetting processes in the detection period, wherein:

the offsetting module comprises an offset capacitor, and the control module is further configured to control the offset capacitor to perform a plurality of times of first offsetting operations on the capacitor to be detected until charges corresponding the base capacitance of the capacitor to be detected are offset in the i-th first offsetting process, each of the plurality of times of first offsetting operations comprising: charging an offset capacitor to a voltage of a voltage source Vcc minus a voltage source Vss; and performing charge offsetting on the capacitor to be detected through the charged offset capacitor; and

the control module is further configured to control the offset capacitor to perform a plurality of times of second offsetting operations on the capacitor to be detected until the charges corresponding the base capacitance of the capacitor to be detected are offset in the j-th second offsetting process, each of the plurality of times of second offsetting operations comprising: charging an offset capacitor to a voltage of a voltage source Vss minus a voltage source Vcc; and performing charge offsetting on the capacitor to be detected through the charged offset capacitor.

13. The circuit according to claim 12 , further comprising a first switching module, wherein switching between the first offsetting process and the second offsetting process is performed under the control of the first switching module.

14. The circuit according to claim 13 , wherein the first switching module comprises at least three first switches, wherein at least one of the first switches is provided in the driving module configured to charge the capacitor to be detected in a first offsetting stage or discharge the capacitor to be detected in a second offsetting stage, and at least two other first switches of the first switches are provided in the offsetting module configured to perform base capacitance offsetting on the capacitor to be detected.

15. The circuit according to claim 12 , wherein the offsetting module charges and discharges the offset capacitor under the control of a third switching module, to perform base capacitance offsetting on the capacitor to be detected in the i-th first offsetting process or the j-th second offsetting process.

16. The circuit according to claim 12 , further comprising a fourth switching module, wherein under the control of the fourth switching module, charge transferring on the capacitor to be detected is performed in the i-th first offsetting process or charge transferring on the capacitor to be detected is performed in the j-th second offsetting process.

17. The circuit according to claim 16 , wherein the fourth switching module comprises at least one fourth switch, and the fourth switch is configured to enable the capacitor to be detected to be in a charge transferring state in the i-th first offsetting process, or enable the capacitor to be detected to be in a charge transferring state in the j-th second offsetting process.

18. The circuit according to claim 12 , wherein N=M, and i=j.