IP Library › Granted Patent US 11,687,420
Granted Patent B2
US 11,687,420 · App. 17/563,641 · Granted Jun 27, 2023

Control method for error handling in a controller, storage medium therefor, controller and storage device

Inventors: Wen Jyh Lin (Zhubei, TW); Yun Chih Huang (Zhubei, TW); Fu Hsiung Lin (Zhubei, TW)
Assignee: SK hynix Inc.
G06F11/2005G06F11/201G06F2201/85
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Quick Facts
Patent No.
US 11,687,420
App. No.
17/563,641
Filed
Dec 28, 2021
Granted
Jun 27, 2023
Kind
B2
Art Unit
2114
USPC
714/56
Abstract

A control method for error handling in a controller, storage medium therefor, controller, and storage device. The controller for use in a first device is capable of linking to a second device according to an interconnection protocol. The control method includes the following steps: handling a first error information by transmitting a negative acknowledgement control (NAC) message to the second device according to the interconnection protocol through the controller, wherein the first error information indicates a first error occurring while the controller performs data reception according to a protocol layer of the interconnection protocol; and setting error handling status data to indicate that error handling is asserted for the first error information so that the controller does not handle sequence number errors occurring after the first error until the error handling status data is set to indicate that the error handling is de-asserted.

Claims (30)

1. A control method for error handling in a controller, the controller for use in a first device capable of linking to a second device according to an interconnection protocol, the control method comprising:

handling first error information by transmitting a negative acknowledgement control (NAC) message to the second device according to the interconnection protocol, wherein the first error information indicates a first error occurring while the controller performs data reception according to a protocol layer of the interconnection protocol; and

setting error handling status data to indicate that error handling is asserted for the first error information so that the controller does not handle sequence number errors occurring after the first error until the error handling status data is set to indicate that the error handling is de-asserted.

2. The control method according to claim 1 , wherein the method further comprises:

discarding second error information indicating a sequence number error according to the error handling status data indicating that error handling is asserted so that the controller transmits no NAC message due to the second error information.

3. The control method according to claim 1 , wherein the method further comprises:

setting the error handling status data to indicate that the error handling is de-asserted when a data message is received to resolve the first error.

4. The control method according to claim 1 , wherein the protocol layer is a Universal Flash Storage InterConnect (UIC) layer.

5. The control method according to claim 1 , wherein the first device is a storage device according to Universal Flash Storage standard.

6. The control method according to claim 5 , wherein the first device is configured to communicate with the second device in an asymmetry power mode.

7. A non-transitory storage medium, which stores program instructions that are capable of causing a storage device to perform the control method for error handling according to claim 1 .

8. A controller, the controller for use in a first device capable of linking to a second device according to an interconnection protocol, the controller comprising:

an error handling module configured to handle first error information by transmitting a negative acknowledgement control (NAC) message to the second device according to the interconnection protocol, wherein the first error information indicates a first error occurring while the controller performs data reception according to a protocol layer of the interconnection protocol; and

an error suppression module configured to set error handling status data to indicate that error handling is asserted for the first error information so that the controller does not handle sequence number errors occurring after the first error until the error handling status data is set to indicate that the error handling is de-asserted.

9. The controller according to claim 8 , wherein the error suppression module is further configured to discard second error information indicating a sequence number error according to the error handling status data indicating that the error handling is asserted so that the error handling module transmits no NAC message due to the second error information.

10. The controller according to claim 8 , wherein the error suppression module is further configured to set the error handling status data to indicate that the error handling is de-asserted when a data message that resolves the first error is received.

11. The controller according to claim 8 , wherein the protocol layer is a Universal Flash Storage InterConnect (UIC) layer.

12. The controller according to claim 8 , wherein the first device is a storage device according to Universal Flash Storage standard.

13. The controller according to claim 12 , wherein the first device is configured to communicate with the second device in an asymmetry power mode.

14. A storage device, capable of linking a host according to an interconnection protocol, the storage device comprising:

a non-volatile memory; and

a memory controller, coupled to the non-volatile memory, for controlling data access to the non-volatile memory, wherein the memory controller is configured to perform a plurality of operations comprising:

handling first error information by transmitting a negative acknowledgement control (NAC) message to the host according to the interconnection protocol, wherein the first error information indicates a first error occurring while the memory controller performs data reception according to a protocol layer of the interconnection protocol; and

setting error handling status data to indicate that error handling is asserted for the first error information so that the memory controller does not handle sequence number errors occurring after the first error until the error handling status data is set to indicate that the error handling is de-asserted.

15. The storage device according to claim 14 , wherein the memory controller is configured to further perform:

discarding second error information indicating a sequence number error according to the error handling status data indicating that the error handling is asserted so that the memory controller transmits no NAC message due to the second error information.

16. The storage device according to claim 14 , wherein the memory controller is configured to further perform:

setting the error handling status data to indicate that the error handling is de-asserted when a data message that resolves the first error is received.

17. The storage device according to claim 14 , wherein the protocol layer is a Universal Flash Storage InterConnect (UIC) layer.

18. The storage device according to claim 14 , wherein the storage device is compliant with Universal Flash Storage standard.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 28, 2021
From: LIN, WEN JYH; HUANG, YUN CHIH; LIN, FU HSIUNG
To: SK HYNIX INC.
Reel/Frame 058491/0760 →
Priority Claims (1)
TW 110107090 · Feb 26, 2021 · national
Continuity (1)
Related Publication 20220276939A1 · Sep 1, 2022
Cited By (6)
US 12,450,136 US 12,512,927 US 12,513,227 US 12,517,791 US 12,524,295 US 12,574,449