Gate-all-around memory devices
View Patent ↗Static Random Access Memory (SRAM) cells and memory structures are provided. An SRAM cell according to the present disclosure includes a first pull-up gate-all-around (GAA) transistor and a first pull-down GAA transistor coupled to form a first inverter, a second pull-up GAA transistor and a second pull-down GAA transistor coupled to form a second inverter, a first pass-gate GAA transistor coupled to an output of the first inverter and an input of the second inverter, a second pass-gate GAA transistor coupled to an output of the second inverter and an input of the first inverter; a first dielectric fin disposed between the first pull-up GAA transistor and the first pull-down GAA transistor, and a second dielectric fin disposed between the second pull-up GAA transistor and the second pull-down GAA transistor.
1. A memory structure, comprising:
a first Static Random Access Memory (SRAM) cell comprising
a first fin-shaped vertical stack over a first p-type well, the first fin-shaped vertical stack comprising a first plurality of nanostructures stacked one over another,
a second fin-shaped vertical stack over an n-type well adjacent the first p-type well, the second fin-shaped vertical stack comprising a second plurality of nanostructures stacked one over another,
a third fin-shaped vertical stack over the n-type well, the third fin-shaped vertical stack comprising a third plurality of nanostructures stacked one over another,
a fourth fin-shaped vertical stack over a second p-type well adjacent the n-type well, the fourth fin-shaped vertical stack comprising a fourth plurality of nanostructures stacked one over another,
a first dielectric fin between the first fin-shaped vertical stack and the second fin-shaped vertical stack,
a second dielectric fin between the second fin-shaped vertical stack and the third fin-shaped vertical stack, and
a third dielectric fin between the third fin-shaped vertical stack and the fourth fin-shaped vertical stack.
2. The memory structure of claim 1 ,
wherein the first dielectric fin is disposed directly over an interface between the first p-type well and the n-type well, and
wherein the third dielectric fin is disposed directly over an interface between the n-type well and the second p-type well.
3. The memory structure of claim 1 , further comprising:
a fourth dielectric fin adjacent to the fourth fin-shaped vertical stack; and
a dielectric gate cut feature disposed on and vertically aligned with the third dielectric fin,
wherein the fourth dielectric fin is disposed over the second p-type well.
4. The memory structure of claim 3 , where each of the first dielectric fin, the second dielectric fin, the third dielectric fin, and the fourth dielectric fin comprises one or more dielectric materials selected from a group consisting of silicon oxycarbide, silicon oxynitride, silicon oxycarbonitride, silicon nitride, aluminum oxide, yittrium oxide, titanium oxide, tantalum oxide, hafnium oxide, and zirconium oxide.
5. The memory structure of claim 3 , further comprising:
a second SRAM cell,
wherein the second SRAM cell is a mirror image of the first SRAM cell with respect to the fourth dielectric fin.
6. The memory structure of claim 5 , wherein the first SRAM cell and the second SRAM cell share the second p-type well.
7. A Static Random Access Memory (SRAM) cell, comprising:
a first fin-shaped vertical stack over a first p-type well, the first fin-shaped vertical stack comprising a first plurality of nanostructures stacked one over another;
a second fin-shaped vertical stack over an n-type well adjacent the first p-type well, the second fin-shaped vertical stack comprising a second plurality of nanostructures stacked one over another;
a third fin-shaped vertical stack over the n-type well, the third fin-shaped vertical stack comprising a third plurality of nanostructures stacked one over another;
a fourth fin-shaped vertical stack over a second p-type well adjacent the n-type well, the fourth fin-shaped vertical stack comprising a fourth plurality of nanostructures stacked one over another;
a first dielectric fin between the first fin-shaped vertical stack and the second fin-shaped vertical stack;
a second dielectric fin between the second fin-shaped vertical stack and the third fin-shaped vertical stack; and
a third dielectric fin between the third fin-shaped vertical stack and the fourth fin-shaped vertical stack.
8. The SRAM cell of claim 7 ,
wherein the first fin-shaped vertical stack includes a first pass-gate transistor and a first pull-down transistor,
wherein the second fin-shaped vertical stack includes a first pull-up transistor,
wherein the third fin-shaped vertical stack includes a second pull-up transistor,
wherein the fourth fin-shaped vertical stack includes a second pass-gate transistor and a second pull-down transistor.
9. The SRAM cell of claim 7 , further comprising:
a fourth dielectric fin adjacent to the first fin-shaped vertical stack; and
a fifth dielectric fin adjacent to the fourth fin-shaped vertical stack.
10. The SRAM cell of claim 9 , wherein the fourth dielectric fin and the fifth dielectric fin define two ends of the SRAM cell.
11. The SRAM cell of claim 9 , wherein the fifth dielectric fin is disposed over the second p-type well.
12. The SRAM cell of claim 9 , further comprising:
a first gate cut dielectric feature disposed on the fourth dielectric fin; and
a second gate cut dielectric feature disposed on the third dielectric fin.
13. The SRAM cell of claim 7 , further comprising:
an isolation feature among the first fin-shaped vertical stack, the second fin-shaped vertical stack, the third fin-shaped vertical stack, and the fourth fin-shaped vertical stack,
wherein each of the first dielectric fin, the second dielectric fin, and the third dielectric fin is disposed over the isolation feature.
14. The SRAM cell of claim 7 , where each of the first dielectric fin, the second dielectric fin, and the third dielectric fin comprises one or more dielectric materials selected from a group consisting of silicon oxycarbide, silicon oxynitride, silicon oxycarbonitride, silicon nitride, aluminum oxide, yittrium oxide, titanium oxide, tantalum oxide, hafnium oxide, and zirconium oxide.
15. The SRAM cell of claim 7 , wherein the first dielectric fin is disposed directly over an interface between the first p-type well and the n-type well.
16. The SRAM cell of claim 7 , wherein the third dielectric fin is disposed directly over an interface between the n-type well and the second p-type well.
17. A memory cell, comprising:
a first vertical stack of nanostructures over a first p-type well;
a second vertical stack of nanostructure over an n-type well adjacent the first p-type well;
a third vertical stack of nanostructures over the n-type well;
a fourth vertical stack of nanostructures over a second p-type well adjacent the n-type well;
a first dielectric fin between the first vertical stack of nanostructures and the second vertical stack of nanostructures;
a second dielectric fin between the second vertical stack of nanostructures and the third vertical stack of nanostructures; and
a third dielectric fin between the third vertical stack of nanostructures and the fourth vertical stack of nanostructures.
18. The memory cell of claim 17 , wherein each of the first dielectric fin, the second dielectric fin, and the third dielectric fin comprises:
a first layer; and
a second layer disposed in the first layer,
wherein a composition of the first layer is different from a composition of the second layer.
19. The memory cell of claim 18 , wherein each of the first dielectric fin, the second dielectric fin, and the third dielectric fin further comprises a cap layer disposed on the first layer and the second layer.
20. The memory cell of claim 17 , further comprising:
a fourth dielectric fin adjacent to the fourth vertical stack of nanostructures,
wherein the fourth dielectric fin is disposed over the second p-type well.