Merged power pad for improving integrated circuit power delivery

1. A method for assembling an integrated circuit (IC) package, comprising:

forming a plurality of dies on a wafer, wherein each die in the plurality of dies includes a plurality of pads formed on the die and exposed on a top surface of the die;

forming at least one post on a first die of the plurality of dies, wherein a first post of the at least one post is constructed to span at least two pads on the first die utilized for power distribution; and

connecting, via the at least one post, the first die to a substrate including one or more redistribution layers (RDLs).

2. The method of claim 1 , wherein the at least two pads are associated with a first common node and are connected to a positive power supply of the first die, and wherein a second post of the at least one post spans two or more additional pads on the first die that are associated with a second common node and that are connected to a negative power supply of the first die.

3. The method of claim 1 , further comprising encapsulating the first die in a polymer material.

4. The method of claim 3 , wherein one or more additional posts formed on the substrate are encapsulated within the polymer material, further comprising grinding or polishing a top surface of the integrated circuit package to expose a top surface of the one or more additional posts.

5. The method of claim 4 , further comprising:

placing solder on the exposed top surface of the one or more additional posts; and

stacking one or more additional packages on top of the IC package.

6. The method of claim 1 , wherein connecting the first die to the substrate comprises:

placing solder on the at least one post;

placing the first die on the substrate; and

reflowing the solder to connect the at least one post to the substrate.

7. The method of claim 1 , wherein connecting the first die on the substrate comprises:

encapsulating the first die in a polymer material;

grinding a top surface of the integrated circuit package to expose a top surface of the at least one post; and

forming the substrate by depositing the one or more RDLs on the top grounded surface of the integrated circuit package utilizing a semi-additive plating process.

8. A method for creating an integrated circuit package, comprising:

forming a die on a wafer, the die includes a plurality of pads formed on the die and exposed on a top surface of the die;

forming at least one post on the die, wherein the at least one post is formed to span at least two of the plurality of pads on the die utilized for power distribution; and

connecting, via the at least one post, the die to a substrate including one or more redistribution layers (RDLs).

9. The method of claim 8 , further including connecting the at least two pads to a positive power supply of the die, and connecting two or more additional pads to a negative power supply of the die.

10. The method of claim 9 , further comprising encapsulating the die in a polymer material.

11. The method of claim 10 , further including removing a top surface of the polymer material to expose a top surface of the one or more additional posts.

12. The method of claim 11 , further comprising:

placing solder on the exposed top surface of the one or more additional posts; and

stacking one or more additional integrated circuits on top of the integrated circuit package.

13. The method of claim 12 , wherein connecting the die to the substrate comprises:

placing solder on the at least one post;

placing the die on the substrate; and

reflowing the solder to connect the at least one post to the substrate.

14. The method of claim 8 , wherein connecting the die on the substrate comprises:

encapsulating the die in a polymer material;

grinding a top surface of the integrated circuit package to expose a top surface of the at least one post; and

forming the substrate by depositing the one or more RDLs on the top ground surface of the integrated circuit package utilizing a semi-additive plating process.

15. A method for assembling an integrated circuit (IC) package, comprising:

forming a substrate on a carrier;

forming a plurality of first posts on the substrate;

form a die on a wafer, the die includes a plurality of pads formed on the die;

forming a plurality of second posts on the die, a least one post the plurality of second posts constructed to span at least two of the plurality of pads on the die and associated with a common node utilized for power distribution; and

connecting, via the at least one post of the plurality of second posts, the die to the substrate including one or more redistribution layers (RDLs).

16. The method of claim 15 , further comprising encapsulating the die in a polymer material.

17. The method of claim 16 , wherein one or more additional posts formed on the substrate are encapsulated within the polymer material, further comprising grinding or polishing a top surface of the integrated circuit package to expose a top surface of the one or more additional posts.

18. The method of claim 17 , further comprising:

placing solder on the exposed top surface of the one or more additional posts; and

stacking one or more additional packages on top of the IC package.

19. The method of claim 15 , wherein connecting the die to the substrate comprises:

placing solder on the plurality of second posts;

placing the die on the substrate; and

reflowing the solder to connect the plurality of second posts to the substrate.

20. The method of claim 15 , wherein connecting the die on the substrate comprises:

encapsulating the die in a polymer material;

grinding a top surface of the integrated circuit package to expose a top surface of the plurality of first posts; and

forming the substrate by depositing the one or more RDLs on the top ground surface of the integrated circuit package utilizing a semi-additive plating process.