Field-plate trench FET and associated method for manufacturing
A field-plate trench FET having a drain region, an epitaxial layer, a source region, a gate conductive layer formed in a trench, a field-plate dielectric layer formed on vertical sidewalls of the trench, a well region formed below the trench, a source contact and a gate contact. When the well region is in direct physical contact with the gate conductive layer, the field-plate trench FET can be used as a normally-on device working depletion mode, and when the well region is electrically isolated from the gate conductive layer by the field-plate layer, the field-plate trench FET can be used as a normally-off device working in an accumulation-depletion mode.
1. A field-plate trench FET, comprising:
a drain region of a first conductivity type;
an epitaxial layer of the first conductivity type formed on the drain region;
a source region of the first conductivity type formed in the epitaxial layer;
a trench filled with a gate conductive layer and a field-plate dielectric layer, wherein the gate conductive layer is formed below a top surface of the source region, and the field-plate dielectric layer is formed on vertical sidewalls of the trench;
a well region of a second conductivity type formed below the trench;
a gate contact formed on the gate conductive layer; and
a source contact formed on the source region; wherein
the well region is in direct physical contact with the gate conductive layer, and a gate control of the field-plate trench FET via the gate conductive layer is configured to be performed with a lateral channel depletion.
2. The field-plate trench FET of claim 1 , wherein when a first bias voltage is applied at the gate contact, the field-plate trench FET is configured to be used as a normally-on device working in a depletion mode.
3. The field-plate trench FET of claim 1 , wherein the field-plate dielectric layer comprises silicon oxide, and the gate conductive layer comprises polysilicon.
4. The field-plate trench FET of claim 1 , wherein the gate conductive layer is electrically isolated from the source region by the field-plate dielectric layer.
5. The field-plate trench FET of claim 1 , wherein the field-plate dielectric layer is adjacent to the source region.
6. The field-plate trench FET of claim 1 , further comprising:
a dielectric layer, formed to cover the trench and the gate contact.
7. The field-plate trench FET of claim 1 , wherein the trench is configured to be a U-shaped trench with higher slope vertical sidewall than 86° sidewall.
8. The field-plate trench FET of claim 1 , wherein the gate conductive layer is formed at a bottom of the source region.
9. The field-plate trench FET of claim 1 , wherein the field-plate dielectric layer is formed between the gate conductive layer and the source region.
10. A field-plate trench FET, comprising:
a drain region of a first conductivity type;
an epitaxial layer of the first conductivity type formed on the drain region;
a source region of the first conductivity type formed in the epitaxial layer;
a trench filled with a gate conductive layer and a field-plate dielectric layer, wherein the field-plate dielectric layer is formed on vertical sidewalls of the trench, and the gate conductive layer is electrically isolated from the source region by the field-plate dielectric layer; and
a well region of a second conductivity type formed below the trench; wherein
the well region is in direct physical contact with the gate conductive layer, and a gate control of the field-plate trench FET via the gate conductive layer is configured to be performed with a lateral channel depletion.
11. The field-plate trench FET of claim 10 , wherein when a first bias voltage is applied at the gate conductive layer, the field-plate trench FET is configured to be used as a normally-on device working in a depletion mode.
12. The field-plate trench FET of claim 11 , wherein the first bias voltage is negative.
13. The field-plate trench FET of claim 10 , wherein the gate conductive layer is formed below a top surface of the source region.
14. The field-plate trench FET of claim 10 , wherein the gate conductive layer is formed below or at a bottom of the source region.
15. The field-plate trench FET of claim 10 , wherein the trench is configured to be a U-shaped trench with higher slope vertical sidewall than 86° sidewall.
16. The field-plate trench FET of claim 10 , wherein the field-plate dielectric layer comprises silicon oxide, and the gate conductive layer comprises polysilicon.
17. The field-plate trench FET of claim 10 , wherein the field-plate dielectric layer is adjacent to the source region.
18. The field-plate trench FET of claim 10 , wherein the field-plate dielectric layer is formed between the gate conductive layer and the source region.