Alternative protocol over physical layer

1. A link controller comprising:

a Peripheral Component Interconnect Express (PCIe) physical layer circuit coupled to a communication link and providing a data path over said communication link;

a first data link layer controller which operates according to a PCIe protocol;

a second data link layer controller which operates according to a Gen-Z protocol;

a multiplexer-demultiplexer coupled to the first data link layer controller and the PCIe physical layer circuit; and

a protocol translation circuit coupled to the multiplexer-demultiplexer and the second data link layer controller, the protocol translation circuit receiving traffic data from the second data link layer controller in a Gen-Z format, encapsulating the Gen-Z format traffic data in a PCIe format, and passing the encapsulated traffic data to the multiplexer-demultiplexer.

2. The link controller of claim 1 , wherein the protocol translation circuit receives an indication from the PCIe physical layer circuit that the communication link is ready to initiate a connection, transmits an indication to the PCIe physical layer circuit to initiate a connection, and during the connection passes only data from the second data link layer controller through the multiplexer-demultiplexer to the PCIe physical layer circuit.

3. The link controller of claim 1 , wherein the protocol translation circuit operates to prepare PCIe-formatted transaction layer packets (TLPs) including data from one or more Gen-Z packets and PCIe framing data.

4. The link controller of claim 3 , wherein the protocol translation circuit operates to format the TLPs such that a TLP transmission does not extend beyond an interval between a selected PCIe skip ordered set (SKP OS) and a subsequent SKP OS required by the PCIe physical layer circuit.

5. The link controller of claim 3 , wherein the protocol translation circuit operates to express the traffic data from the one or more Gen-Z packets with PCIe symbols.

6. The link controller of claim 1 , wherein the protocol translation circuit receives a request from the PCIe physical layer circuit to provide a gap in data transmission for inserting a PCIe skip ordered set (SKP OS), and in response, halts packet transmission to allow the PCIe physical layer circuit to insert a SKP OS.

7. The link controller of claim 1 further comprising a protocol selection circuit which selectively controls the PCIe physical layer circuit to:

transmit and receive alternative protocol negotiation information over the communication link; and,

in response to receiving the alternative protocol negotiation information, cause the multiplexer-demultiplexer to selectively couple the PCIe physical layer circuit to the second data link layer controller.

8. A method comprising:

selectively causing a multiplexer-demultiplexer to couple a Peripheral Component Interconnect Express (PCIe) physical layer circuit through a protocol translation circuit to a Gen-Z data link layer controller; and

at the protocol translation circuit, receiving traffic data from the Gen-Z data link layer controller in a Gen-Z format, encapsulating the Gen-Z format traffic data in a PCIe format, and passing the encapsulated traffic data through the multiplexer-demultiplexer to the PCIe physical layer circuit; and

transmitting the encapsulated traffic data over a communication link from the PCIe physical layer circuit.

9. The method of claim 8 , further comprising, at the protocol translation circuit, receiving an indication from the PCIe physical layer circuit that the communication link is ready to initiate a connection, transmitting an indication to the PCIe physical layer circuit to initiate a connection, and during the connection passing only data from the Gen-Z data link layer controller through the multiplexer-demultiplexer to the PCIe physical layer circuit.

10. The method of claim 8 , further comprising, at the protocol translation circuit, preparing PCIe-formatted transaction layer packets (TLPs) including data from one or more Gen-Z packets and PCIe framing data.

11. The method of claim 10 , further comprising, at the protocol translation circuit, expressing the data from the one or more Gen-Z packets with PCIe symbols.

12. The method of claim 10 , further comprising, at the protocol translation circuit, formatting the TLPs such that a TLP transmission does not extend beyond an interval between a selected PCIe skip ordered set (SKP OS) and a subsequent SKP OS required by the PCIe physical layer circuit.

13. The method of claim 10 , further comprising, at the protocol translation circuit, receiving a request from the PCIe physical layer circuit to provide a gap in data transmission for inserting a PCIe skip ordered set (SKP OS), and in response, halting packet transmission to allow the PCIe physical layer circuit to insert a SKP OS.

14. The method of claim 8 , further comprising,

transmitting and receiving alternative protocol negotiation information over the communication link; and,

in response to receiving the alternative protocol negotiation information, causing the multiplexer-demultiplexer to couple the PCIe physical layer circuit through a protocol translation circuit to the Gen-Z data link layer controller.

15. A data processing platform comprising:

a central processing unit;

a dual-protocol link controller coupled to said central processing unit and comprising:

a Peripheral Component Interconnect Express (PCIe) physical layer circuit coupled to a communication link and providing a data path over said communication link;

a first data link layer controller which operates according to a PCIe protocol;

a second data link layer controller which operates according to a Gen-Z protocol;

a multiplexer-demultiplexer coupled to the first data link layer controller and the PCIe physical layer circuit; and

a protocol translation circuit to the multiplexer-demultiplexer and the second data link layer controller, the protocol translation circuit receiving traffic data from the second data link layer controller in a Gen-Z format, encapsulating the Gen-Z format traffic data to a PCIe format, and passing the encapsulated traffic data to the multiplexer-demultiplexer.

16. The data processing platform of claim 15 , wherein the protocol translation circuit receives an indication from the PCIe physical layer circuit that the communication link is ready to initiate a connection, transmits an indication to the PCIe physical layer circuit to initiate a connection, and during the connection passes only data from the second data link layer controller through the multiplexer-demultiplexer to the PCIe physical layer circuit.

17. The data processing platform of claim 15 , wherein the protocol translation circuit operates to prepare PCIe-formatted transaction layer packets (TLPs) including data from one or more Gen-Z packets and PCIe framing data.

18. The data processing platform of claim 17 , wherein the protocol translation circuit operates to format the TLPs such that a TLP transmission does not extend beyond an interval between a selected PCIe skip ordered set (SKP OS) and a subsequent SKP OS required by the PCIe physical layer circuit.

19. The data processing platform of claim 17 , wherein the protocol translation circuit receives a request from the PCIe physical layer circuit to provide a gap in data transmission for inserting a PCIe skip ordered set (SKP OS), and in response, halts packet transmission to allow the PCIe physical layer circuit to insert a SKP OS.

20. The data processing platform of claim 15 , further comprising:

a memory module comprising a memory, a media controller coupled to the memory, and an interface controller coupled to the media controller and the communication link, a second PCIe physical layer circuit communicatively coupled to a second Gen-Z data link layer controller through a second protocol translation circuit.