Die yield assessment based on pattern-failure rate simulation
This application discloses a computing system to identify structures of an integrated circuit capable of being fabricated utilizing a lithographic mask described by mask layout data and to generate process windows for the identified structures based, at least in part, on the mask layout data and a failure definition for the identified structures. The computing system utilizes process windows for the identified structures to determine failure rates for the identified structures based on a distribution of the manufacturing parameters. The computing system determines frequency of occurrences for the identified structures from the mask layout data and generates a die yield metric for the integrated circuit by aggregating the failure rates for the identified structures based on the frequency of occurrences for the identified structures in the integrated circuit. These increases in yield of the integrated circuit allow manufacturers to produce more units per fixed processing cost of the wafer.
1. A method comprising:
identifying, by a computing system, structures of an integrated circuit capable of being fabricated utilizing a lithographic mask described by mask layout data;
determining, by the computing system, failure rates for the identified structures by:
generating the process windows for the identified structures based, at least in part, on a lithographic response of the mask layout data and a failure definition for the integrated circuit, and
integrating a distribution of manufacturing parameters during fabrication over the generated process windows for the identified structures;
determining, by the computing system, frequency of occurrences for the identified structures in the integrated circuit from the mask layout data; and
generating, by the computing system, a die yield metric for the integrated circuit based, at least in part, on the failure rates for the identified structures and frequency of occurrences for the identified structures in the integrated circuit.
2. The method of claim 1 , further comprising applying, by the computing system, a probability density function corresponding to the distribution of the manufacturing parameters during fabrication to the process windows for the identified structures to generate the failure rates for the identified structures.
3. The method of claim 1 , wherein generating the die yield metric for the integrated circuit further comprises aggregating the failure rates for the identified structures based, at least in part, on the frequency of occurrences for the identified structures in the integrated circuit.
4. The method of claim 1 , further comprising setting, by the computing system, values for the manufacturing parameters for use during fabrication of the integrated circuit based, at least in part, on the die yield metric for the integrated circuit.
5. The method of claim 1 , further comprising predicting, by the computing system, an error tolerance from a critical dimension for the structures in the integrated circuit based, at least in part, on the die yield metric.
6. The method of claim 1 , wherein the manufacturing parameters correspond to a focus of light exposed through the lithographic mask onto the integrated circuit and an exposure dose for the light.
7. A system comprising:
a memory device configured to store machine-readable instructions; and
a computing system including one or more processing devices, in response to executing the machine-readable instructions, configured to:
identify structures of an integrated circuit capable of being fabricated utilizing a lithographic mask described by mask layout data;
determine failure rates for the identified structures by:
generating the process windows for the identified structures based, at least in part, on a lithographic response of the mask layout data and a failure definition for the integrated circuit, and
integrating a distribution of manufacturing parameters during fabrication over the generated process windows for the identified structures;
determine frequency of occurrences for the identified structures in the integrated circuit from the mask layout data; and
generate a die yield metric for the integrated circuit based, at least in part, on the failure rates for the identified structures and frequency of occurrences for the identified structures in the integrated circuit.
8. The system of claim 7 , wherein the one or more processing devices, in response to executing the machine-readable instructions, are configured to apply a probability density function corresponding to the distribution of the manufacturing parameters during fabrication to the process windows for the identified structures to generate the failure rates for the identified structures.
9. The system of claim 7 , wherein the one or more processing devices, in response to executing the machine-readable instructions, are configured to aggregate the failure rates for the identified structures based, at least in part, on the frequency of occurrences for the identified structures in the integrated circuit, which generates the die yield metric for the integrated circuit.
10. The system of claim 7 , wherein the one or more processing devices, in response to executing the machine-readable instructions, are configured to set values for the manufacturing parameters for use during fabrication of the integrated circuit based, at least in part, on the die yield metric for the integrated circuit.
11. The system of claim 7 , wherein the one or more processing devices, in response to executing the machine-readable instructions, are configured to predict an error tolerance from a critical dimension for the structures in the integrated circuit based, at least in part, on the die yield metric.
12. An apparatus including a memory device storing instructions configured to cause one or more processing devices to perform operations comprising:
identifying structures of an integrated circuit capable of being fabricated utilizing a lithographic mask described by mask layout data;
determining failure rates for the identified structures by:
generating the process windows for the identified structures based, at least in part, on a lithographic response of the mask layout data and a failure definition for the integrated circuit, and
integrating a distribution of manufacturing parameters during fabrication over the generated process windows for the identified structures;
determining frequency of occurrences for the identified structures in the integrated circuit from the mask layout data; and
generating a die yield metric for the integrated circuit based, at least in part, on the failure rates for the identified structures and frequency of occurrences for the identified structures in the integrated circuit.
13. The apparatus of claim 12 , wherein the instructions are configured to cause one or more processing devices to perform operations further comprising applying a probability density function corresponding to the distribution of the manufacturing parameters during fabrication to the process windows for the identified structures to generate the failure rates for the identified structures.
14. The apparatus of claim 12 , wherein generating the die yield metric for the integrated circuit further comprises aggregating the failure rates for the identified structures based, at least in part, on the frequency of occurrences for the identified structures in the integrated circuit.
15. The apparatus of claim 12 , wherein the instructions are configured to cause one or more processing devices to perform operations further comprising setting values for the manufacturing parameters for use during fabrication of the integrated circuit based, at least in part, on the die yield metric for the integrated circuit.
16. The apparatus of claim 12 , wherein the instructions are configured to cause one or more processing devices to perform operations further comprising predicting an error tolerance from a critical dimension for the structures in the integrated circuit based, at least in part, on the die yield metric.
17. The apparatus of claim 12 , wherein the manufacturing parameters correspond to a focus of light exposed through the lithographic mask onto the integrated circuit and an exposure dose for the light.