IP Library Granted Patent US 11,699,068
Granted Patent B2
US 11,699,068 · App. 16/831,085 · Granted Jul 11, 2023

Imaging device, imaging module, electronic device, and imaging system

Inventors: Takayuki Ikeda (Atsugi, JP); Takahiro Fukutome (Atsugi, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
G06N3/0675G06N3/04G06N3/065H01L27/14609H01L27/14616H01L27/14618H04N23/57H04N25/75H04N25/77H01L27/1225H01L27/1464H01L27/14627H01L27/14636H01L27/14689H01L29/7869H01L29/78633H01L29/78648H01L29/78696H01L2224/48091
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Quick Facts
Patent No.
US 11,699,068
App. No.
16/831,085
Granted
Jul 11, 2023
Kind
B2
Abstract

An imaging device connected to a neural network is provided. An imaging device having a neuron in a neural network includes a plurality of first pixels, a first circuit, a second circuit, and a third circuit. Each of the plurality of first pixels includes a photoelectric conversion element. The plurality of first pixels is electrically connected to the first circuit. The first circuit is electrically connected to the second circuit. The second circuit is electrically connected to the third circuit. Each of the plurality of first pixels generates an input signal of the neuron. The first circuit, the second circuit, and the third circuit function as the neuron. The third circuit includes an interface connected to the neural network.

Claims (48)

1. An imaging device comprising a plurality of circuits,

wherein the plurality of circuits each comprises:

a plurality of pixels each comprising a circuit configured to generate a first signal and a first operation circuit configured to generate a second signal by multiplying the first signal by a weight coefficient; and

a second operation circuit configured to perform an arithmetic operation using a plurality of second signals output from the plurality of pixels,

wherein the first operation circuit is configured to be supplied with a potential corresponding to the weight coefficient,

wherein the second operation circuit is located below the plurality of pixels, and

wherein in each of the plurality of circuits, the plurality of pixels are directly connected to the second operation circuit.

2. The imaging device according to claim 1 ,

wherein the plurality of pixels in each of the plurality of circuits is arranged in p rows and q columns, and

wherein each of p and q is a natural number of 2 or more.

3. The imaging device according to claim 1 ,

wherein the second operation circuit comprises a circuit configured to execute at least a part of a product-sum operation.

4. The imaging device according to claim 3 ,

wherein the second operation circuit further comprises a circuit configured to determine a signal output from the circuit configured to execute at least the part of the product-sum operation.

5. The imaging device according to claim 1 ,

wherein the second operation circuit corresponds to at least a part of a neural network.

6. The imaging device according to claim 1 ,

wherein the plurality of circuits is arranged in x rows and y columns, and

wherein each of x and y is a natural number of 2 or more.

7. The imaging device according to claim 1 ,

wherein output signals of the plurality of circuits are configured to be processed in parallel.

8. The imaging device according to claim 1 ,

wherein each of the plurality of circuits is configured to output a digital signal.

9. A chip including the imaging device according to claim 1 .

10. The imaging device according to claim 1 ,

wherein the circuit configured to generate the first signal comprises a photoelectric conversion element and a transistor,

wherein the first signal is in accordance with a signal output from the photoelectric conversion element,

wherein the transistor is configured to control output of the first signal,

wherein a second layer including the transistor is located over a first layer including the first operation circuit, and

wherein a third layer including the photoelectric conversion element is located over the second layer.

11. The imaging device according to claim 1 ,

wherein the plurality of circuits each comprises a third operation circuit, and

wherein the third operation circuit is configured to determine a third signal output from the second operation circuit.

12. The imaging device according to claim 11 ,

wherein the first to third operation circuits correspond to at least a part of a neural network.

13. The imaging device according to claim 11 ,

wherein the plurality of circuits comprises a first circuit and a second circuit, and

wherein the third operation circuit in the first circuit and the third operation circuit in the second circuit are connected to a same scan line.

14. An imaging device comprising a plurality of pixels, each of the plurality of pixels comprising:

a circuit configured to generate a first signal; and

a first operation circuit configured to generate an output signal by multiplying the first signal by a weight coefficient,

wherein the circuit configured to generate the first signal comprises a photoelectric conversion element and a transistor,

wherein the first signal is in accordance with a signal output from the photoelectric conversion element,

wherein the transistor is configured to control output of the first signal,

wherein a second layer including the transistor is located over a first layer including the first operation circuit,

wherein a third layer including the photoelectric conversion element is located over the second layer,

wherein the first operation circuit is configured to be supplied with a potential corresponding to the weight coefficient, and

wherein the first operation circuit is located below the circuit configured to generate a first signal.

Priority Claims (2)
JP 2016-153192 · Aug 3, 2016 · national
JP 2016-153194 · Aug 3, 2016 · national
Continuity (2)
Continuation 15661318 · Jul 27, 2017
Related Publication 20200226457A1 · Jul 16, 2020
Cited By (2)
US 12,396,181 US 12,659,621