Semiconductor memory device performing read operation, and method for the semiconductor memory device

1. A semiconductor memory device comprising:

a cell string including at least one drain select transistor that is connected to a bit line, at least one source select transistor that is connected to a common source line, and a plurality of memory cells that are connected between the drain select transistor and the source select transistor; and

a peripheral circuit configured to perform a read operation on a selected memory cell among the plurality of memory cells,

wherein the peripheral circuit is configured to:

read data that is stored in the selected memory cell by applying a read voltage to a selected word line among word lines that are connected to the plurality of memory cells and by applying a pass voltage to unselected word lines

apply a turn-on voltage to a drain select line that is connected to the drain select transistor;

apply a turn-off voltage to a source select line that is connected to the source select transistor while applying the turn-on voltage to the drain select line; and

apply a boosting prevention voltage to the bit line while applying an equalizing voltage to the word lines.

2. The semiconductor memory device of claim 1 , wherein the boosting prevention voltage is the same voltage as a precharge voltage that is applied to the bit line at a beginning of the read operation.

3. The semiconductor memory device of claim 1 , wherein the boosting prevention voltage is a voltage greater than a precharge voltage that is applied to the bit line at a beginning of the read operation.

4. The semiconductor memory device of claim 1 , wherein the equalizing voltage is greater than the read voltage and less than the pass voltage.

5. The semiconductor memory device of claim 1 , wherein the equalizing voltage is the same voltage as the pass voltage.

6. A semiconductor memory device comprising:

a cell string including at least one drain select transistor that is connected to a bit line, at least one source select transistor that is connected to a common source line, and a plurality of memory cells that are connected between the drain select transistor and the source select transistor; and

a peripheral circuit configured to perform a read operation on a selected memory cell among the plurality of memory cells,

wherein the peripheral circuit is configured to:

read data that is stored in the selected memory cell by applying a read voltage to a selected word line among word lines that are connected to the plurality of memory cells and by applying a pass voltage to unselected word lines;

apply a turn-on voltage to a source select line that is connected to the source select transistor;

apply a turn-off voltage to a drain select line that is connected to the drain select transistor while applying the turn-on voltage to the source select line; and

apply the boosting prevention voltage to the common source line while applying the equalizing voltage to the word lines.

7. A method of operating a semiconductor memory device comprising a cell string including at least one drain select transistor that is connected to a bit line, at least one source select transistor that is connected to a common source line, and a plurality of memory cells that are connected between the drain select transistor and the source select transistor, the method comprising:

applying a read voltage to a selected word line among a plurality of word lines that are respectively connected to the plurality of memory cells and applying a pass voltage to unselected word lines;

applying a turn-on voltage to a drain select line that is connected to the drain select transistor;

applying a turn-off voltage to a source select line that is connected to the source select transistor;

transmitting a boosting prevention voltage to the drain select transistor through the bit line; and

applying an equalizing voltage to the plurality of word lines.

8. The method of claim 7 , further comprising, before applying the read voltage to the selected word line among the plurality of word lines that are respectively connected to the plurality of memory cells and applying the pass voltage to the unselected word lines:

applying a precharge voltage to the bit line,

wherein the boosting prevention voltage is the same voltage as the precharge voltage.

9. The method of claim 7 , further comprising, before applying the read voltage to the selected word line among the plurality of word lines that are respectively connected to the plurality of memory cells and applying the pass voltage to the unselected word lines:

applying a precharge voltage to the bit line,

wherein the boosting prevention voltage is greater than the precharge voltage.

10. The method of claim 7 , wherein the equalizing voltage is greater than the read voltage and less than the pass voltage.

11. The method of claim 7 , wherein the equalizing voltage is the same voltage as the pass voltage.

12. A method of operating a semiconductor memory device comprising a cell string including at least one drain select transistor that is connected to a bit line, at least one source select transistor that is connected to a common source line, and a plurality of memory cells that are connected between the drain select transistor and the source select transistor, the method comprising:

applying a read voltage to a selected word line among a plurality of word lines that are respectively connected to the plurality of memory cells and applying a pass voltage to unselected word lines;

applying a turn-on voltage to a source select line that is connected to the source select transistor;

applying a turn-off voltage to a drain select line that is connected to the drain select transistor;

transmitting a boosting prevention voltage to the source select transistor through the common source line; and

applying the equalizing voltage to the plurality of word lines.