IP Library › Granted Patent US 11,699,626
Granted Patent B2
US 11,699,626 · App. 17/355,831 · Granted Jul 11, 2023

Semiconductor package and method of manufacturing the same

Inventors: Jun-young Oh (Seoul, KR); Hyun-ki Kim (Anyang-si, KR); Sang-soo Kim (Cheonan-si, KR); Seung-hwan Kim (Anyang-si, KR); Yong-kwan Lee (Hwaseong-si, KR)
Assignee: Samsung Electronics Co., Ltd.
H01L23/295H01L21/561H01L21/565H01L23/291H01L23/3114H01L23/3128H01L23/5283H01L24/09H01L24/17H01L24/97
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 11,699,626
App. No.
17/355,831
Granted
Jul 11, 2023
Kind
B2
Abstract

A semiconductor package includes a package substrate, at least one semiconductor chip mounted on the package substrate, and a molding member that surrounds the at least one semiconductor chip. The molding member includes fillers. Each of the fillers includes a core and a coating layer that surrounds the core. The core includes a non-electromagnetic material and the coating layer includes an electromagnetic material. The molding member includes regions respectively have different distributions of the fillers.

Claims (60)

1. A method of manufacturing a semiconductor package, the method comprising:

mounting at least one semiconductor chip on top of a package substrate;

coating a molding material including fillers including an electromagnetic material on the package substrate to surround the at least one semiconductor chip,

moving the fillers in a certain direction in the molding material by applying an electric field or a magnetic field to the molding material; and

forming a molding member to surround the at least one semiconductor chip by curing the molding material, wherein

the molding member covers a bottom surface, a side surface, and top surfaces of the at least one semiconductor chip, wherein

the mounting the semiconductor chip includes mounting the semiconductor chip on the package substrate using solder bumps and the moving the fillers includes applying an electric field or a magnetic field such that the fillers are moved to be placed around each of the solder bumps and placed in a relatively high distribution in a region between the semiconductor chip and the package substrate in the molding material, or

the moving the fillers includes applying an electric field or a magnetic field such that the fillers are spaced apart from the semiconductor chip and placed in a relatively high distribution in the molding material at a peripheral region of the semiconductor chip, or

the moving the fillers includes applying an electric field or a magnetic field such that the fillers are spaced apart from the semiconductor chip and placed in a relatively high distribution in an upper region of the molding material.

2. The method of claim 1 , wherein

the moving the fillers includes the applying an electric field or a magnetic field such that the fillers are spaced apart from the semiconductor chip and placed in a relatively high distribution in the molding material at a peripheral region of the semiconductor chip.

3. The method of claim 1 , wherein

the moving the fillers includes the applying an electric field or a magnetic field such that the fillers are spaced apart from the semiconductor chip and placed in a relatively high distribution in an upper region of the molding material.

4. A method of manufacturing a semiconductor package, the method comprising:

mounting at least one semiconductor chip on a package substrate;

coating a molding material including fillers including an electromagnetic material on the package substrate to surround the at least one semiconductor chip,

moving the fillers in a certain direction in the molding material by applying an electric field or a magnetic field to the molding material; and

forming a molding member by curing the molding material, wherein

in the moving of the fillers, the electric field or the magnetic field is applied to the fillers such that the fillers are moved in a direction in which warpage of the package substrate is alleviated, and

in the forming the molding member, coefficients of thermal expansion in different regions of the molding member vary according to a distribution of the fillers.

5. The method of claim 4 , wherein

a coefficient of thermal expansion in an upper region of the molding material is different than a coefficient of thermal expansion in a lower region of the molding material after the applying the electric field or the magnetic field.

6. The method of claim 1 , wherein

a processing time of the applying the electric field or the magnetic field to the molding material during the moving the fillers in the certain direction and a processing time of the curing the molding material at least partially overlap each other.

7. The method of claim 1 , wherein

a shape of the fillers includes at least one of a sphere, a platelet, or a fiber.

8. A method of manufacturing a semiconductor package, the method comprising:

mounting at least one semiconductor chip on a package substrate;

coating a molding material including fillers including an electromagnetic material on the package substrate to surround the at least one semiconductor chip,

moving the fillers in a certain direction in the molding material by applying an electric field or a magnetic field to the molding material; and

forming a molding member by curing the molding material, wherein

the fillers each include a core and a coating layer that surrounds the core,

the core includes a non-electromagnetic material, and

the coating layer includes an electromagnetic material.

9. The method of claim 8 , wherein, during the coating the molding material,

the molding material includes the fillers distributed in an epoxy material,

the core includes silicon oxide or aluminum oxide, and

the coating layer includes one of a metal, a metal oxide, a polymer, a polymer electrolyte, or a carbon composite material.

10. The method of claim 8 , wherein, during the coating the molding material,

the fillers include first fillers and second fillers,

the first fillers are configured to react relatively strongly to the electric field compared to the second fillers,

the second fillers are configured to react relatively weakly to the electric field compared to the first fillers.

11. The method of claim 10 , wherein

the electromagnetic material in the coating layer of the first fillers and the electromagnetic material in the coating layer of the second fillers include a polymer electrolyte, and

a thickness of the coating layer of the first fillers is different from a thickness of the coating layer of the second fillers.

12. The method of claim 8 , wherein, during the coating the molding material,

the fillers include first fillers and second fillers,

the first fillers are configured to have a force in a first direction in response to the magnetic field,

the second fillers are configured have a force in a second direction that is opposite to the first direction in response to the magnetic field.

13. The method of claim 12 , wherein

the electromagnetic material in the coating layer of the first fillers is a ferromagnetic material, and

the electromagnetic material in the coating layer of the second fillers is a diamagnetic material.

14. The method of claim 1 , wherein

the molding member includes a first region and a second region,

the first region has a first concentration of the fillers,

the second region has a second concentration of the fillers that is less than the first concentration,

the second region is over the first region and extends over the at least one semiconductor chip, and

the at least one semiconductor chip is on the first region.

15. The method of claim 1 , wherein

the mounting of the semiconductor chip includes mounting the semiconductor chip on the package substrate using solder bumps and the moving the fillers includes the applying an electric field or a magnetic field such that the fillers are moved to be placed around each of the solder bumps and placed in a relatively high distribution in a region between the semiconductor chip and the package substrate in the molding material.

Priority Claims (1)
KR 10-2018-0090056 · Aug 1, 2018 · national
Continuity (2)
Division 16357732 · Mar 19, 2019
Related Publication 20210320043A1 · Oct 14, 2021