Semiconductor package including redistributed layer and method for fabrication therefor

1. A semiconductor package comprising:

a redistribution layer;

a semiconductor chip electrically connected to the redistribution layer, and disposed on an upper surface of the redistribution layer;

a plurality of solder balls disposed on the upper surface of the redistribution layer spaced apart from the semiconductor chip and electrically connected to the redistribution layer;

an interposer electrically connected to the plurality of solder balls, and disposed directly on upper surfaces of the plurality of solder balls;

an encapsulant layer encapsulating the semiconductor chip, and side surfaces and a portion of the upper surface of the redistribution layer under the interposer; and

an underfill layer filling a space between a lower surface of the interposer and an upper surface of the encapsulant layer,

wherein the encapsulant layer includes a side surface encapsulant region surrounding the side surfaces of the redistribution layer, and a first region surrounding the semiconductor chip and covering the upper surface of the redistribution layer,

wherein the side surface encapsulant region and the first region are continuously integrated with each other without a boundary therebetween and integrally formed through a single process,

wherein the underfill layer contacts the lower surface of the interposer, the upper surface of the encapsulant layer, an upper surface of the semiconductor chip, and side surfaces of the plurality of solder balls, and

wherein upper portions of the plurality of solder balls are surrounded by the underfill layer and lower portions of the plurality of solder balls are surrounded by the encapsulant layer and contact the encapsulant layer.

2. The semiconductor package of claim 1 , wherein the redistribution layer includes a plurality of dielectric layers except for a core layer.

3. The semiconductor package of claim 2 , wherein the plurality of dielectric layers includes a first redistribution layer, a second redistribution layer, a third redistribution layer, and a fourth redistribution layer, and

a height of a vertical cross-section of each of the first redistribution layer, the second redistribution layer, the third redistribution layer, and the fourth redistribution layer is 15 μm.

4. The semiconductor package of claim 1 , further comprising a connection structure disposed on a lower surface of the semiconductor chip,

wherein the semiconductor chip is electrically connected to the redistribution layer through the connection structure.

5. The semiconductor package of claim 4 , wherein the connection structure includes a solder bump or a metal pad electrically connected to the redistribution layer.

6. The semiconductor package of claim 1 , wherein a width of the upper surface of the redistribution layer is 10 mm to 14 mm, and a length of the upper surface of the redistribution layer is 10 mm to 14 mm.

7. The semiconductor package of claim 1 , wherein, in a vertical cross-section of the semiconductor package, a height from an upper surface of the interposer to the upper surface of the semiconductor chip is 140 μm.

8. The semiconductor package of claim 1 , wherein, in a vertical cross-section of the semiconductor package, a width of the upper surface of the semiconductor chip is 7 mm to 11 mm, and a length of the upper surface of the semiconductor chip is 7 mm to 11 mm.

9. The semiconductor package of claim 1 , wherein, in a vertical cross-section of the semiconductor package, a width of one side of the side surface encapsulant region is 140 μm.

10. The semiconductor package of claim 1 , wherein, in a vertical cross-section of the semiconductor package, a height of the redistribution layer is 60 μm.

11. A semiconductor package comprising:

a redistribution layer;

a semiconductor chip electrically connected to the redistribution layer, and disposed on an upper surface of the redistribution layer;

a plurality of inner solder balls electrically connected to the redistribution layer, and disposed on the upper surface of the redistribution layer;

an interposer electrically connected to the plurality of inner solder balls, and disposed on an upper surface of the plurality of inner solder balls;

an encapsulant layer encapsulating the semiconductor chip, side surfaces of the redistribution layer and a bottom surface and a portion of the upper surface of the redistribution layer under the interposer; and

an underfill layer filling a space between a lower surface of the interposer and an upper surface of the encapsulant layer,

wherein the encapsulant layer includes a side surface encapsulant region surrounding the side surfaces of the redistribution layer, a first region surrounding the semiconductor chip and covering the upper surface of the redistribution layer, and a lower surface encapsulant region covering the bottom surface of the redistribution layer,

wherein the side surface encapsulant region and the first region are continuously integrated with each other without a boundary therebetween and integrally formed through a single process,

wherein the underfill layer contacts the lower surface of the interposer, the upper surface of the encapsulant layer, an upper surface of the semiconductor chip, and side surfaces of the plurality of inner solder balls, and

wherein upper portions of the plurality of inner solder balls are surrounded by the underfill layer and lower portions of the plurality of inner solder balls are surrounded by the encapsulant layer and contact the encapsulant layer.

12. The semiconductor package of claim 11 , wherein, in a vertical cross-section of the semiconductor package, a height of the lower surface encapsulant region is 50 μm.

13. The semiconductor package of claim 11 , wherein the lower surface encapsulant region includes an external solder ball region for disposing a plurality of external solder balls.

14. The semiconductor package of claim 13 , wherein the external solder ball region includes a plurality of circular holes.

15. The semiconductor package of claim 14 , wherein each of the plurality of circular holes includes an upper circle formed on an upper surface of the lower surface encapsulant region, and a lower circle formed on a lower surface of the lower surface encapsulant region.

16. The semiconductor package of claim 15 , wherein a diameter of the lower circle is larger than a diameter of the upper circle.

17. The semiconductor package of claim 16 , wherein the diameter of the upper circle is 300 μm.

18. The semiconductor package of claim 16 , wherein the diameter of the lower circle is 360 μm.

19. A semiconductor package comprising:

a redistribution layer including a plurality of dielectric layers and a plurality of metal distribution lines;

a semiconductor chip disposed on an upper surface of the redistribution layer;

a connection structure between the redistribution layer and the semiconductor chip;

a plurality of inner solder balls disposed on the upper surface of the redistribution layer, the plurality of inner solder balls being spaced apart from the semiconductor chip;

an encapsulant layer encapsulating the semiconductor chip, the plurality of inner solder balls, and a side surface and a portion of the upper surface of the redistribution layer;

an interposer disposed on the semiconductor chip, the plurality of inner solder balls, and the encapsulant layer;

an underfill between the semiconductor chip and the interposer; and

a plurality of external solder balls disposed on a bottom surface of the redistribution layer,

wherein the underfill contacts a lower surface of the interposer, an upper surface of the encapsulant layer, an upper surface of the semiconductor chip, and side surfaces of the plurality of inner solder balls,

wherein the encapsulant layer includes a side surface encapsulant region surrounding the side surfaces of the redistribution layer, and a first region surrounding the semiconductor chip and covering the upper surface of the redistribution layer,

wherein the side surface encapsulant region and the first region are continuously integrated with each other without a boundary therebetween and integrally formed through a single process, and

wherein upper portions of the plurality of inner solder balls are surrounded by the underfill and lower portions of the plurality of inner solder balls are surrounded by the encapsulant layer and contact the encapsulant layer.