Electrostatic protection circuit

1. An electrostatic protection circuit, connected with an internal circuit and comprising:

a first circuit, a first diode connected in parallel with the first circuit, a second circuit, and a second diode connected in parallel with the second circuit, wherein

the first circuit is connected between a power supply pad and an internal circuit input terminal, and the second circuit is connected between the internal circuit input terminal and a ground pad;

the first circuit comprises at least two third diodes, the second circuit comprises at least two fourth diodes, and the number of the third diodes and the number of the fourth diodes are adjusted such that conduction voltages of the first circuit and the second circuit are greater than an operating voltage of an input pad and less than a breakdown voltage of an electronic device connected to the internal circuit input terminal; and

the first circuit and the second circuit are diode-triggered silicon controlled rectifier (DTSCR) circuits.

2. The electrostatic protection circuit of claim 1 , wherein

the first circuit comprises a first positive-negative-positive (PNP) transistor and a first negative-positive-negative (NPN) transistor, an emitter of the first PNP transistor is connected with the power supply pad, a base of the first PNP transistor is connected with a collector of the first NPN transistor and then connected with the internal circuit input terminal through the at least two third diodes connected in series, a collector of the first PNP transistor is connected with a base of the first NPN transistor and then connected with the internal circuit input terminal through a first resistor, an emitter of the first NPN transistor is connected with the internal circuit input terminal, and a negative electrode of the first diode is connected with the power supply pad; and

the second circuit comprises a second PNP transistor and a second NPN transistor, an emitter of the second PNP transistor is connected with the internal circuit input terminal, a base of the second PNP transistor is connected with a collector of the second NPN transistor and then connected with the ground pad through the at least two fourth diodes connected in series, a collector of the second PNP transistor is connected with a base of the second NPN transistor and then connected with the ground pad through a second resistor, and a positive electrode of the second diode is connected with the ground pad.

3. The electrostatic protection circuit of claim 2 , further comprising: a fifth diode connected between the power supply pad and the input pad, and a sixth diode connected between the input pad and the ground pad,

wherein a positive electrode of the fifth diode is connected with the input pad, and a positive electrode of the sixth diode is connected with the ground pad.

4. The electrostatic protection circuit of claim 3 , further comprising: an input resistor connected between the input pad and the internal circuit input terminal.

5. The electrostatic protection circuit of claim 4 , wherein the ground pad and the power supply pad are both located on a bare chip, a first well, a second well and a third well are disposed in a substrate of the bare chip, the substrate is a positive-type (P-type) substrate, and the first well, the second well and the third well are all negative (N) wells;

the first well comprises a first P-type heavily doped region and a first N-type heavily doped region, and the power supply pad is electrically connected with the first P-type heavily doped region;

the second well comprises a second P-type heavily doped region and a second N-type heavily doped region, and the second P-type heavily doped region is electrically connected with the first N-type heavily doped region; and

the third well comprises a third P-type heavily doped region and a third N-type heavily doped region, the third P-type heavily doped region is electrically connected with the second N-type heavily doped region, and the internal circuit input terminal is electrically connected with the third N-type heavily doped region.

6. The electrostatic protection circuit of claim 5 , wherein the substrate further includes a seventh N-type heavily doped region and a seventh P-type heavily doped region, both of which are electrically connected with the internal circuit input terminal.

7. The electrostatic protection circuit of claim 6 , wherein the first P-type heavily doped region, the first well and the substrate form the first PNP transistor; and

the first well, the substrate and the seventh N-type heavily doped region form the first NPN transistor.

8. The electrostatic protection circuit of claim 6 , wherein the first resistor is formed between the first well and the seventh P-type heavily doped region.

9. The electrostatic protection circuit of claim 5 , wherein the first diode is formed between the third well and the first well.

10. The electrostatic protection circuit of claim 5 , wherein a fourth well, a fifth well and a sixth well are disposed in the substrate, and the fourth well, the fifth well and the sixth well are all N wells;

the fourth well comprises a fourth P-type heavily doped region and a fourth N-type heavily doped region, and the internal circuit input terminal is electrically connected with the fourth P-type heavily doped region;

the fifth well comprises a fifth P-type heavily doped region and a fifth N-type heavily doped region, and the fifth P-type heavily doped region is electrically connected with the fourth N-type heavily doped region; and

the sixth well comprises a sixth P-type heavily doped region and a sixth N-type heavily doped region, the sixth P-type heavily doped region is electrically connected with the fifth N-type heavily doped region, and the ground pad is electrically connected with the sixth N-type heavily doped region.

11. The electrostatic protection circuit of claim 10 , wherein the substrate further includes an eighth N-type heavily doped region and an eighth P-type heavily doped region, both of which are electrically connected with the ground pad.

12. The electrostatic protection circuit of claim 11 , wherein

the fourth P-type heavily doped region, the fourth well and the substrate form the second PNP transistor; and

the fourth well, the substrate and the eighth N-type heavily doped region form the second NPN transistor.

13. The electrostatic protection circuit of claim 11 , wherein the second resistor is formed between the fourth well and the eighth P-type heavily doped region.

14. The electrostatic protection circuit of claim 10 , wherein the second diode is formed between the sixth well and the fourth well.

15. The electrostatic protection circuit of claim 10 , wherein multiple N wells are disposed between the fifth well and the sixth well, and one of the at least two fourth diodes is formed in each N well.

16. The electrostatic protection circuit of claim 5 , wherein multiple N wells are disposed between the second well and the third well, and one of the at least two third diodes is formed in each N well.