Monolithic integration of a thin film transistor over a complimentary transistor

1. An apparatus comprising:

a first device comprising an enhancement mode III-N heterostructure field effect transistor (HFET);

a second device over the first device, wherein the second device comprises a depletion mode thin film transistor, wherein the second device includes a layer comprising an oxide semiconductor extending laterally from a source terminal of the second device to a drain terminal of the second device, and a gate stack coupled to the layer; and

a connector to couple a source terminal of the first device to the drain terminal of the second device, or couple a drain terminal of the first device to the source terminal of the second device.

2. The apparatus of claim 1 , wherein the gate stack is coupled to a backside of the layer, and the source and the drain terminals of the second device are coupled to a frontside of the layer.

3. The apparatus of claim 1 , further comprising:

an inverter circuit that includes:

a driver comprising the first device, and

a load comprising the second device,

wherein the first device is in series with the second device.

4. The apparatus of claim 1 , wherein the gate stack of the second device is between:

the first device, and

the source and drain terminals of the second device.

5. The apparatus of claim 1 , further comprising:

one or more levels of metal between the first device and the second device, wherein the connector includes at least one of the one or more levels of metal.

6. The apparatus of claim 1 , wherein the gate stack of the second device is in contact with the layer comprising the oxide semiconductor.

7. The apparatus of claim 1 , wherein the gate stack is in contact with a first side of the layer, and the source and the drain terminals of the second device are in contact with a second side of the layer that is opposite the first side.

8. The apparatus of claim 1 , wherein the gate stack is coupled to a frontside of the layer comprising the oxide semiconductor, and the source and the drain terminals of the second device are coupled to a backside of the layer comprising the oxide semiconductor.

9. The apparatus of claim 1 , wherein the layer comprising the oxide semiconductor is a channel region of the second device, and wherein the layer has a thickness in the range of 5-20 nanometers (nm).

10. An apparatus comprising:

a first device that is a III-N field effect transistor; and

a second device above the first device,

wherein the second device comprises (i) a source terminal and a drain terminal, (ii) a body comprising a semiconductor material including a metal and oxygen, the body extending laterally from the source terminal of the second device to the drain terminal of the second device, and (ii) a gate stack coupled to the body,

wherein a source terminal of the first device is coupled to the drain terminal of the second device, or a drain terminal of the first device is coupled to the source terminal of the second device, and

wherein the first device is one of an enhancement mode transistor or a depletion mode transistor, and the second device is the other of the enhancement mode transistor or the depletion mode transistor.

11. The apparatus of claim 10 , wherein:

the first device is an enhancement mode III-N heterostructure field effect transistor (HFET); and

the second device is a depletion mode thin film transistor.

12. The apparatus of claim 10 , wherein the first device comprises a channel layer, the channel layer comprising gallium and nitrogen.

13. The apparatus of claim 12 , wherein the first device comprises:

a polarization layer adjacent to the channel layer,

wherein the channel layer comprises a two-dimensional electron gas (2DEG) region near a junction of the polarization layer and the channel layer.

14. The apparatus of claim 10 , wherein the gate stack is in contact with a first side of the body, and the source and the drain terminals of the second device are in contact with a second side of the body that is opposite the first side.

15. The apparatus of claim 10 , further comprising:

one or more levels of metal between the first device and the second device,

wherein

using the one or more levels of metal, one of (i) the source terminal of the first device is coupled to the drain terminal of the second device, or (ii) the drain terminal of the first device is coupled to the source terminal of the second device.

16. The apparatus of claim 10 , comprising:

an inverter circuit that includes:

a driver comprising the first device, and

a load comprising the second device.

17. An integrated circuit comprising:

a first device comprising an enhancement mode III-N heterostructure field effect transistor (HFET) that includes gallium and nitrogen;

a second device over the first device, the second device comprising a depletion mode thin film transistor (TFT) that includes (i) a body comprising oxide semiconductor, (ii) a source or drain terminal above the body, and (iii) a gate stack below the body; and

a connector to couple a first terminal of the first device to a first terminal of the second device.

18. The integrated circuit of claim 17 , wherein the gate stack is a first gate stack, and wherein the HFET comprises a second gate stack.

19. The integrated circuit of claim 17 , wherein the a gate stack of the first device includes a first high-k gate dielectric, and the gate stack of the TFT includes a second high-k gate dielectric, and wherein the HFET and the TFT are operatively coupled in an inverter circuit configuration.

20. The integrated circuit of claim 17 , wherein: the HFET comprises a polarization layer between a gate structure and a layer of gallium nitride; and the TFT comprises the source terminal on the oxide semiconductor and the drain terminal on the oxide semiconductor.