Gate structure and method
A device includes a substrate, a semiconductor channel over the substrate, and a gate structure over and laterally surrounding the semiconductor channel. The gate structure includes a first dielectric layer over the semiconductor channel, a first work function metal layer over the first dielectric layer, a first protection layer over the first work function metal layer, a second protection layer over the first protection layer, and a metal fill layer over the second protection layer.
1. A device, comprising:
a substrate;
a semiconductor channel over the substrate; and
a gate structure over and laterally surrounding the semiconductor channel, comprising:
a first dielectric layer over the semiconductor channel;
a first work function metal layer over and in physical contact with the first dielectric layer;
a first protection layer over the first work function metal layer;
a second protection layer over the first protection layer; and
a metal fill layer over the second protection layer,
a third protection layer over the first protection layer and the second protection layer; and
a capping layer in physical contact with the first protection layer and the first work function metal layer.
2. The device of claim 1 , wherein the gate structure further comprises a barrier layer between the first work function metal layer and the first dielectric layer.
3. The device of claim 1 , wherein:
the first protection layer comprises Si, Ge, SiGe, Al, Ti, or Hf; and
the second protection layer comprises a metal or a conductive metal oxide.
4. The device of claim 1 , wherein the gate structure further comprises:
an interfacial layer between the first dielectric layer and the semiconductor channel.
5. The device of claim 1 , wherein the gate structure is further over and surrounding a second semiconductor channel between the first semiconductor channel and the substrate.
6. The device of claim 1 , wherein the first protection layer is an in-situ silane passivation layer.
7. A device, comprising:
a first gate structure comprising:
a first dielectric layer over a first semiconductor channel;
a first work function metal layer over the first dielectric layer;
a first protection layer over the first work function metal layer;
a second protection layer over the first protection layer; and
a first metal fill layer over the second protection layer; and
a second gate structure comprising:
a second dielectric layer over a second semiconductor channel;
a first barrier layer over the second dielectric layer;
a second work function metal layer over the first barrier layer;
a third protection layer over the second work function metal layer; and
a second metal fill layer over the third protection layer;
wherein the first protection layer and the third protection layer are in-situ silane passivation layers.
8. The device of claim 7 , wherein the first semiconductor channel and the second semiconductor channel are formed in the same material layer.
9. The device of claim 7 , wherein the first semiconductor channel is silicon and the second semiconductor channel is SiGe.
10. The device of claim 7 , wherein the first gate structure further comprises a fourth protection layer over the second protection layer.
11. The device of claim 7 , wherein the second gate structure further comprises a second barrier layer between the first barrier layer and the second work function metal layer.
12. A method, comprising:
forming a first dielectric layer over a first channel;
forming a first barrier layer over the first dielectric layer;
forming a first work function metal layer over the first dielectric layer;
removing the first barrier layer;
forming a first protection layer over the first work function metal layer;
forming a second protection layer over the first protection layer; and
forming a first metal fill layer over the second protection layer;
wherein the first work function metal layer is formed over the first barrier layer.
13. The method of claim 12 , further comprising:
forming a third protection layer over the second protection layer before forming the first metal fill layer.
14. The method of claim 12 , wherein removing the first barrier layer is by an artificial-intelligence (AI) controlled atomic layer etch (ALE) process.
15. The method of claim 12 , further comprising:
forming an interfacial layer over the first channel, wherein the first dielectric layer is formed over the interfacial layer;
forming a capping layer over the first work function metal layer, wherein the first protection layer is formed over the capping layer; and
forming a glue layer over the second protection layer, wherein the first metal fill layer is formed over the glue layer.
16. The method of claim 12 , further comprising:
forming the first dielectric layer over a second channel located over a different region of a substrate than the first channel; and
removing the second protection layer from over the second channel while the second protection layer over the first channel is not exposed.
17. The method of claim 16 , further comprising forming a second barrier layer over the first barrier layer on the second channel and over the first dielectric layer on the first channel.
18. The method of claim 17 , further comprising removing the second barrier layer from over the first channel.
19. The method of claim 18 , further comprising:
forming a third protection layer on the second channel and over the second protection layer on the first channel; and
removing the third protection layer from over the second channel.
20. The method of claim 12 , wherein the first protection layer is an in-situ silane passivation layer.