Semiconductor device with gate dielectric formed using selective deposition
A semiconductor device includes source and a drain above a substrate and spaced apart along a first direction, and a semiconductor channel extending between the source and the drain. The semiconductor device further includes gate spacers, an interfacial layer, and a metal gate structure. The gate spacers are disposed on the semiconductor channel and spaced apart by a spacer-to-spacer distance along the first direction. The interfacial layer is on the semiconductor channel. The interfacial layer extends a length along the first direction, and the length is less than a minimum of the spacer-to-spacer distance along the first direction. The metal gate structure is over the interfacial layer.
1. A semiconductor device comprising:
a source and a drain above a substrate and spaced apart along a first direction;
a semiconductor channel extending between the source and the drain;
gate spacers disposed on the semiconductor channel and spaced apart by a spacer-to-spacer distance along the first direction;
an interfacial layer on the semiconductor channel, the interfacial layer extending a length along the first direction, the length being less than a minimum of the spacer-to-spacer distance along the first direction;
a void region between the interfacial layer and one of the gate spacers; and
a metal gate structure over the interfacial layer.
2. The semiconductor device of claim 1 , further comprising:
a high-k dielectric layer over the interfacial layer, the high-k dielectric layer extending a length along the first direction, and the length of the high-k dielectric layer being less than the minimum of the spacer-to-spacer distance.
3. The semiconductor device of claim 1 , further comprising:
a high-k dielectric layer over the interfacial layer, wherein end surfaces of the high-k dielectric layer are respectively aligned with end surfaces of the interfacial layer.
4. The semiconductor device of claim 1 , wherein along the first direction, the metal gate structure has a width greater than the length of the interfacial layer.
5. The semiconductor device of claim 1 , further comprising:
a high-k dielectric layer under the metal gate structure, wherein along the first direction, the metal gate structure has a width greater than a length of the high-k dielectric layer.
6. The semiconductor device of claim 1 , wherein the metal gate structure has a curved surface bordering the void region.
7. The semiconductor device of claim 1 , wherein the metal gate structure comprises a first work function metal layer and a second work function metal layer over the first work function metal layer, and the first and second work function metal layers form a curved interface directly above the void region.
8. The semiconductor device of claim 1 , wherein the semiconductor channel is in a fin structure extending from the substrate.
9. The semiconductor device of claim 1 , wherein the semiconductor channel is in a nanowire enclosed within the interfacial layer.
10. The semiconductor device of claim 1 , further comprising:
a high-k dielectric layer over the interfacial layer, wherein the high-k dielectric layer has a side surface bordering the void region.
11. A semiconductor device comprising:
a channel region over a substrate;
source and drain regions respectively on opposite sides of the channel region;
a metal gate structure over the channel region; and
a gate dielectric layer under the metal gate structure, wherein in a cross-sectional view along a plane containing cross-sections of the source and drain regions, the metal gate structure wraps around three sides of the gate dielectric layer.
12. The semiconductor device of claim 11 , further comprising:
a gate spacer separated from the gate dielectric layer by the metal gate structure.
13. The semiconductor device of claim 12 , wherein a distance from the gate spacer to the gate dielectric layer is about 0.5 nm to about 3 nm.
14. The semiconductor device of claim 11 , further comprising:
an interfacial layer below the gate dielectric layer, wherein the interfacial layer and the gate dielectric layer have a same length when viewed in the cross-sectional view along the plane containing the cross-sections of the source and drain regions.
15. The semiconductor device of claim 14 , wherein the metal gate structure is in contact with opposite end surfaces of the interfacial layer.
16. A semiconductor device comprising:
a channel region over a substrate;
source and drain regions respectively on opposite sides of the channel region;
a metal gate structure over the channel region;
first and second gate spacers on opposite sidewalls of the metal gate structure; and
a gate dielectric layer under the metal gate structure, wherein in a cross-sectional view along a plane containing cross-sections of the source and drain regions, the gate dielectric layer resembles a rectangular pattern, the rectangular pattern having a first side facing the first gate spacer but spaced apart from the first gate spacer, and a second side facing the second gate spacer but spaced apart from the second gate spacer.
17. The semiconductor device of claim 16 , wherein the metal gate structure is in contact with the first and second sides of the rectangular pattern of the gate dielectric layer.
18. The semiconductor device of claim 16 , further comprising:
an interfacial layer under the gate dielectric layer, wherein in the cross-sectional view, the interfacial layer resembles a rectangular pattern having a same length as the gate dielectric layer.
19. The semiconductor device of claim 18 , wherein the rectangular pattern of the interfacial layer has a first side facing the first gate spacer but spaced apart from the first gate spacer, and a second side facing the second gate spacer but spaced apart from the second gate spacer.
20. The semiconductor device of claim 16 , wherein the metal gate structure is in contact with the first and second gate spacers.