Thin film transistor and fabrication method thereof, array substrate and fabrication method thereof, and display panel

1. A method for fabricating a thin film transistor, comprising: forming an active layer on a substrate, the active layer comprising a first region, a second region, and a third region; forming a gate insulating layer on a side of the active layer away from the substrate; forming a gate electrode on a side of the gate insulating layer away from the active layer, wherein an orthographic projection of the first region of the active layer on the substrate does not overlap with an orthographic projection of the gate insulating layer on the substrate and an orthographic projection of the gate electrode on the substrate, an orthographic projection of the second region of the active layer on the substrate overlaps with the orthographic projection of the gate insulating layer on the substrate but does not overlap with the orthographic projection of the gate electrode on the substrate, and an orthographic projection of the third region of the active layer on the substrate overlaps with both the orthographic projection of the gate insulating layer on the substrate and the orthographic projection of the gate electrode on the substrate; and performing ion implantation on the active layer from a side of the gate electrode away from the active layer, so that the first region of the active layer is formed into a heavily doped region, the second region of the active layer is formed into a lightly doped region, and the third region of the active layer is formed into an active region; wherein forming the gate insulating layer further comprises forming a plurality of through holes penetrating the gate insulating layer in a region of the gate insulating layer not overlapping with the gate electrode in a direction perpendicular to the substrate, and the plurality of through holes have an aperture in a range of 1 to 4 μm.

2. The method of claim 1 , wherein an energy of the ion implantation is 10 to 100 KeV, and a dose of the ion implantation is less than 2×10 18 atom/cm 3 .

3. The method of claim 1 , wherein a doping concentration of the lightly doped region ranges from 1×10 12 to 1×10 14 atom/cm 2 , and a doping concentration of the heavily doped region ranges from 1×10 14 to 1×10 16 atom/cm 2 .

4. The method of claim 1 , wherein the active layer is made of low temperature polysilicon.

5. The method of claim 1 , wherein the plurality of through holes are uniformly distributed, and a total open area of all the through holes is less than 30% of an area of the lightly doped region.

6. The method of claim 1 , wherein a width between a boundary of the lightly doped region close to the active region and a boundary of the lightly doped region close to the heavily doped region ranges from 1.5 to 6 μm.

7. The method of claim 1 , wherein a common boundary between the lightly doped region and the active region is formed to be aligned with a boundary of the gate electrode.

8. The method of claim 1 , wherein a common boundary between the heavily doped region and the lightly doped region is formed to be aligned with a boundary of the gate insulating layer.

9. The method of claim 1 , wherein the gate electrode is made of one or an alloy material of two or more of copper, aluminum, molybdenum, titanium, chromium and tungsten; the gate insulating layer is made of silicon nitride or silicon oxide.

10. The method of claim 4 , wherein forming the active layer on the substrate comprises:

forming a pattern of an amorphous silicon active film on the substrate; and

crystallizing the pattern of the amorphous silicon active film by laser to form the active layer of low temperature polysilicon.

11. The method of claim 1 , wherein forming the gate insulating layer on the side of the active layer away from the substrate, and forming the gate electrode on the side of the gate insulating layer away from the active layer comprise:

forming a gate insulating film on the side of the active layer away from the substrate;

forming a gate film on a side of the gate insulating film away from the active layer;

forming a first photoresist layer on a side of the gate film away from the gate insulating film;

etching the gate film and the gate insulating film to remove portions of the gate film and the gate insulating film which are not shielded by the first photoresist layer so as to form the gate insulating layer;

forming a second photoresist layer on the side of the gate film away from the gate insulating layer; and

etching the gate film to remove a portion of the gate film which is not shielded by the second photoresist layer so as to form the gate electrode.

12. The method of claim 11 , further comprising:

forming a third photoresist layer on a side of the gate electrode away from the gate insulating layer, wherein a plurality of micro holes are formed in a region of the third photoresist layer which overlaps with the lightly doped region in a direction perpendicular to the substrate; and

etching the gate insulating layer to form a plurality of through holes penetrating the gate insulating layer in a region of the gate insulating layer which does not overlap with the gate electrode in the direction perpendicular to the substrate.

13. The method of claim 12 , wherein after the ion implantation is performed, the method further comprises:

forming an interlayer insulating layer on the side of the gate electrode away from the active layer, and forming a first via hole and a second via hole in the interlayer insulating layer, wherein the first via hole and the second via hole expose the heavily doped region; and

forming a source electrode and a drain electrode on a side of the interlayer insulating layer away from the gate electrode, wherein the source electrode is connected to the heavily doped region through the first via hole, and the drain electrode is connected to the heavily doped region through the second via hole.

14. A thin film transistor, comprising: a substrate; an active layer on the substrate, the active layer comprising a heavily doped region, a lightly doped region, and an active region; a gate insulating layer on a side of the active layer away from the substrate; and a gate electrode on a side of the gate insulating layer away from the active layer, wherein an orthographic projection of the heavily doped region on the substrate does not overlap with an orthographic projection of the gate insulating layer on the substrate and an orthographic projection of the gate electrode on the substrate, an orthographic projection of the lightly doped region on the substrate overlaps with the orthographic projection of the gate insulating layer on the substrate but does not overlap with the orthographic projection of the gate electrode on the substrate, and an orthographic projection of the active region on the substrate overlaps with both the orthographic projection of the gate insulating layer on the substrate and the orthographic projection of the gate electrode on the substrate, and a common boundary between the lightly doped region and the active region is aligned with a boundary of the gate electrode, and a common boundary between the heavily doped region and the lightly doped region is aligned with a boundary of the gate insulating layer; wherein the gate insulating layer further comprises a plurality of through holes penetrating the gate insulating layer in a region of the gate insulating layer not overlapping with the gate electrode in a direction perpendicular to the substrate, and the plurality of through holes have an aperture in a range of 1 to 4 μm.

15. The thin film transistor of claim 14 , wherein a doping concentration of the lightly doped region ranges from 1×10 12 to 1×10 14 atom/cm 2 , and a doping concentration of the heavily doped region ranges from 1×10 14 to 1×10 16 atom/cm 2 .

16. The thin film transistor of claim 14 , further comprising:

an interlayer insulating layer on a side of the gate electrode away from the active layer, a first via hole and a second via hole being in the interlayer insulating layer and exposing the heavily doped region, and

a source electrode and a drain electrode on a side of the interlayer insulating layer away from the gate electrode, wherein the source electrode is connected to the heavily doped region through the first via hole, and the drain electrode is connected to the heavily doped region through the second via hole.

17. A method for fabricating an array substrate, comprising:

forming a thin film transistor in the array substrate by adopting the method of claim 1 .

18. An array substrate, comprising the thin film transistor of claim 14 .

19. A display panel, comprising the array substrate of claim 18 .