Quantum dot devices with fins
Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a substrate and a quantum well stack disposed on the substrate. The quantum well stack may include a quantum well layer and a back gate, and the back gate may be disposed between the quantum well layer and the substrate.
1. A quantum dot device, comprising:
a base;
a first fin extending away from the base, wherein the first fin includes a first quantum well layer;
a plurality of first gates over the first fin, wherein the plurality of first gates extends away from the first fin in a direction perpendicular to a longitudinal axis of the first fin;
a second fin extending away from the base, wherein the second fin includes a second quantum well layer and wherein projections of the first and second fins onto a plane parallel to the base are parallel; and
a plurality of second gates over the second fin, wherein the plurality of second gates extends away from the second fin in a direction perpendicular to a longitudinal axis of the second fin,
wherein:
the first gates are arranged in an arrangement on the first fin, and individual ones of the first gates correspond to individual ones of the second gates such that the second gates are arranged in an analogous arrangement on the second fin.
2. The quantum dot device of claim 1 , wherein the first and second fins are spaced apart by a distance between 100 and 250 nanometers.
3. The quantum dot device of claim 1 , further comprising:
an insulating material in contact with sidewalls of the first fin, wherein a dimension of the insulating material in a direction away from the sidewalls of the first fin is at least 100 nanometers.
4. The quantum dot device of claim 1 , wherein an individual first gate of the plurality of first gates includes a gate dielectric, and a barrier layer is between the first quantum well layer and the gate dielectric.
5. The quantum dot device of claim 1 , wherein a layer that includes silicon and oxygen is between the first quantum well layer and an individual first gate of the plurality of first gates.
6. The quantum dot device of claim 1 , wherein a spacer material is present between an individual first gate of the plurality of first gates and an individual second gate of the plurality of second gates.
7. The quantum dot device of claim 1 , wherein individual ones of the first gates do not extend over the second fin.
8. The quantum dot device of claim 1 , wherein:
the quantum dot device is a quantum computing device,
the quantum computing device includes a quantum processing device, a non-quantum processing device, and a memory device,
the quantum processing device includes the base, the first fin, the second fin, the plurality of first gates, and the plurality of second gates,
the non-quantum processing device is coupled to the quantum processing device and is to control voltages applied to one or more of the first gates and the second gates during operation of the quantum processing device, and
the memory device is to store data generated during operation of the quantum processing device.
9. The quantum dot device of claim 8 , further comprising:
a cooling apparatus to maintain a temperature of the quantum processing device below 5 degrees Kelvin.
10. The quantum dot device of claim 8 , wherein the memory device is to store instructions for a quantum computing algorithm to be executed by the quantum processing device.
11. The quantum dot device of claim 1 , wherein the first gates do not contact sidewalls of the first fin.
12. A quantum dot device, comprising:
a base;
a first fin extending away from the base and including a first quantum well layer;
a second fin extending away from the base and including a second quantum well layer;
a plurality of first gates over the first fin, wherein the plurality of first gates extends away from the first fin in a direction perpendicular to a longitudinal axis of the first fin; and
a plurality of second gates over the second fin, wherein the plurality of second gates extends away from the second fin in a direction perpendicular to a longitudinal axis of the second fin,
wherein:
projections of the first and second fins onto a plane parallel to the base are parallel,
an insulating material is between the first fin and the second fin, and
at least one of the first gates does not contact sidewalls of the first fin.
13. The quantum dot device of claim 12 , wherein individual ones of the first gates include a gate stack that includes at least a gate metal, where the gate stack is absent from sidewalls of the first fin.
14. The quantum dot device of claim 12 , wherein individual ones of the first gates do not extend over the second fin.
15. A quantum dot device, comprising:
a base;
a first fin extending away from the base, wherein the first fin includes a first quantum well layer;
a second fin extending away from the base, wherein the second fin includes a second quantum well layer;
a plurality of first gate lines over different portions of a top surface of the first fin, wherein the first gate lines are parallel to one another and bottom surfaces of the first gate lines are parallel to an upper surface of the base, and each of the first gate lines extends away from the first fin in a direction perpendicular to a longitudinal axis of the first fin; and
a plurality of second gate lines over different portions of a top surface of the second fin, wherein the second gate lines are parallel to one another and bottom surfaces of the second gate lines are parallel to the upper surface of the base, and each of the second gate lines extends away from the second fin in a direction perpendicular to a longitudinal axis of the second fin,
wherein:
the longitudinal axis of the first fin is parallel to the longitudinal axis of the second fin,
the plurality of first gate lines includes at least three of the first gate lines,
the plurality of second gate lines includes at least three of the second gate lines,
a first one of the at least three of the first gate lines and a first one of the at least three of the second gate lines are along a first line that is parallel to the base,
a second one of the at least three of the first gate lines and a second one of the at least three of the second gate lines are along a second line that is parallel to the base and parallel to the first line, and
a third one of the at least three of the first gate lines and a third one of the at least three of the second gate lines are along a third line that is parallel to the base and parallel to the second line.
16. The quantum dot device of claim 15 , further comprising an insulating material between:
the first one of the at least three of the first gate lines and the first one of the at least three of the second gate lines,
the second one of the at least three of the first gate lines and the second one of the at least three of the second gate lines, and
the third one of the at least three of the first gate lines and the third one of the at least three of the second gate lines.
17. The quantum dot device of claim 15 , further comprising an insulating material, wherein:
each of the first fin and the second fin includes a first doped region, a second doped region, a first sidewall extending between the first doped region and the second doped region, and a second sidewall extending between the first doped region and the second doped region, the second sidewall being opposite the first sidewall,
the second sidewall of the first fin is between the first sidewall of the first fin and the first sidewall of the second fin,
the first sidewall of the second fin is between the second sidewall of the first fin and the second sidewall of the second fin, and
the insulating material is between the second sidewall of the first fin and the first sidewall of the second fin.
18. The quantum dot device of claim 17 , further comprising:
a first spacer at an end of the first one of the at least three of the first gate lines,
a second spacer at an end of the first one of the at least three of the second gate lines, and
a further insulating material between the first spacer and the second spacer,
wherein each of the first spacer, the second spacer, and the further insulating material is over the insulating material that is between the second sidewall of the first fin and the first sidewall of the second fin.
19. The quantum dot device of claim 18 , wherein the first spacer is opposite the second spacer.
20. The quantum dot device of claim 18 , wherein the end of the first one of the at least three of the first gate lines is opposite the end of the first one of the at least three of the second gate lines.
21. The quantum dot device of claim 18 , wherein:
the first gate lines are over a continuous portion of the first quantum well layer between the first doped region and the second doped region of the first fin, and
the second gate lines are over a continuous portion of the second quantum well layer between the first doped region and the second doped region of the second fin.
22. A quantum dot device, comprising:
a base;
a first fin extending away from the base and including a first quantum well layer;
a second fin extending away from the base and including a second quantum well layer;
a plurality of first gates over the first fin, wherein the plurality of first gates extends away from the first fin in a direction perpendicular to a longitudinal axis of the first fin;
a plurality of second gates over the second fin, wherein the plurality of second gates extends away from the second fin in a direction perpendicular to a longitudinal axis of the second fin; and
an insulating material in contact with sidewalls of the first fin, wherein a dimension of the insulating material in a direction away from the sidewalls of the first fin is at least 100 nanometers.
23. The quantum dot device of claim 22 , wherein at least one of the second gates does not contact sidewalls of the second fin.
24. The quantum dot device of claim 12 , wherein:
the quantum dot device is a quantum computing device,
the quantum computing device includes a quantum processing device, a non-quantum processing device, and a memory device,
the quantum processing device includes the base, the first fin, the second fin, the plurality of first gates, and the plurality of second gates,
the non-quantum processing device is coupled to the quantum processing device and is to control voltages applied to one or more of the first gates and the second gates during operation of the quantum processing device, and
the memory device is to store data generated during operation of the quantum processing device.
25. The quantum dot device of claim 24 , wherein the memory device is to store instructions for a quantum computing algorithm to be executed by the quantum processing device.
26. The quantum dot device of claim 14 , wherein:
the quantum dot device is a quantum computing device,
the quantum computing device includes a quantum processing device, a non-quantum processing device, and a memory device,
the quantum processing device includes the base, the first fin, the second fin, the plurality of first gate lines, and the plurality of second gate lines,
the non-quantum processing device is coupled to the quantum processing device and is to control voltages applied to one or more of the first gate lines and the second gate lines during operation of the quantum processing device, and
the memory device is to store data generated during operation of the quantum processing device.
27. The quantum dot device of claim 26 , wherein the memory device is to store instructions for a quantum computing algorithm to be executed by the quantum processing device.
28. The quantum dot device of claim 22 , wherein:
the quantum dot device is a quantum computing device,
the quantum computing device includes a quantum processing device, a non-quantum processing device, and a memory device,
the quantum processing device includes the base, the first fin, the second fin, the plurality of first gates, and the plurality of second gates,
the non-quantum processing device is coupled to the quantum processing device and is to control voltages applied to one or more of the first gates and the second gates during operation of the quantum processing device, and
the memory device is to store data generated during operation of the quantum processing device.
29. The quantum dot device of claim 28 , wherein the memory device is to store instructions for a quantum computing algorithm to be executed by the quantum processing device.